XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 378

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
378
Timing Characteristics of 2:1 SDR Serialization
Table 8-11: OSERDES Switching Characteristics (Continued)
In
X-Ref Target - Figure 8-17
Clock Event 1
On the rising edge of CLKDIV, the word AB is driven from the FPGA logic to the D1 and
D2 inputs of the OSERDES (after some propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word AB is sampled into the OSERDES from the D1 and
D2 inputs.
Clock Event 3
The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDES. This
latency is consistent with the
CLK cycle.
Combinatorial
T
T
OSCO_OQ
OSCO_TQ
Figure
CLKDIV
CLK
OQ
D1
D2
Event 1
8-17, the timing of a 2:1 SDR data serialization is illustrated.
Figure 8-17: OSERDES Data Flow and Latency in 2:1 SDR Mode
Symbol
Clock
Event 2
Clock
www.xilinx.com
B
A
Table 8-10
Asynchronous Reset to OQ
Asynchronous Reset to TQ
Clock
Event 3
A
listing of a 2:1 SDR mode OSERDES latency of one
C
D
B
C
E
F
Description
D
E
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
F
UG190_8_17_100307