XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 6

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
05/09/08
09/23/08
12/02/08
01/09/09
03/19/09
Date
Version
4.2
4.3
4.4
4.5
4.6
Revised clock routing resources in
Removed example Figure 2-10 on
Corrected note 1 in
Added
Clarified Note 7 in
in Banks 1 and 2.
Added the TXT platform to
Chapter 2: Revised
(Default), page
Chapter 3: Updated
Chapter 4: Updated
Chapter 6: Labeled all the DCI_18 standards consistently in
Replaced the link to the
Chapter 8: Updated CLKB in
page
Chapter 2: Changed “edge” to “half” in
on
Chapter 4: Added new text and equation to
1 to
Chapter 5: Changed RAM#XM to RAM#M in
Chapter 6: Corrected PCI acronym definition in
Component Interconnect), page
standard in
Chapter 7: Added mode to caption of
Chapter 8: Added statement about shared resources between OCLK and CLK in
Speed Clock for Strobe-Based Memory Interfaces - OCLK, page
Chapter 4: Revised the paragraph below
Chapter 6: Added IBUFDS_DIFF_OUT to the list of primitive names for differential I/O
standards in
IBUFDS_DIFF_OUT, page
Chapter 7: In the Verilog code segment for bidirectional IODELAY on
the setting of RST.
Chapter 3: Added reference to the Virtex-5 FPGA Configuration Guide in
Primitive, page
Chapter 4: In the second paragraph of
configuration” after READ_FIRST.
Chapter 5: In the third sentence of the second paragraph of
page
SRL32 in
Chapter 6: Inserted sentence about at least one I/O being configured as DCI to the
paragraph after
page
Table 4-19, page
357.
178, changed “slices” to “LUTs”. Removed MC31 and SHIFTOUT from the bottom
Legal Block RAM and FIFO Combinations, page
51,
Figure 5-19, page
page
SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination, page
Virtex-5 FPGA SelectIO Primitives, page
66.
93.
Figure 6-4, page
52, and
DCI in Virtex-5 Device I/O
Reset Input - RST, page 53
Table 4-5, page
Jitter Filter, page
Write Modes, page
148.
www.xilinx.com
Full Device SSO
page
235.
193.
Table
Table 8-1, page 355
53.
247. Added to the description of the SSTL18_II_T_DCI
220.
1-5,
page
BUFGCTRL to DCM, page
124.
94.
Figure 7-7, page 323
Table
Write Modes, page
Revision
76.
117, and
IBUFG – Global Clock Input Buffer
Calculator.
Equation 4-1
2-1, and
Almost Empty Flag, page
Figure 5-32, page
and
Standards. Master DCI is not supported
PCI-X, PCI-33, PCI-66 (Peripheral
Asynchronous Clocking, page
and
System-Synchronous Setting
Table
High-Speed Clock Input - CLKB,
233. Added new section
on
171.
page
117, added “in ECC
5-2.
for clarification.
Look-Up Table (LUT),
Table 6-39
UG190 (v5.3) May 17, 2010
73.
146.
212.
357.
page
146. Added note
and
293.
PLL_ADV
333, corrected
Table
description
119.
High-
6-40.