XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 64

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Clock Management Technology
64
Input Clock Requirements
Input Clock Changes
The clock input of the DCM can be driven either by an IBUFG/IBUFGDS, IBUF,
BUFGMUX, or a BUFGCTRL. Since there is no dedicated routing between an IBUF and a
DCM clock input, using an IBUF causes additional input delay that is not compensated by
the DCM and performance can not be guaranteed.
The DCM output clock signal is essentially a delayed version of the input clock signal. It
reflects any instability on the input clock in the output waveform. The DCM input clock
requirements are specified in the Virtex-5 FPGA Data Sheet.
Once locked, the DCM can tolerate input clock period variations of up to the value
specified by CLKIN_PER_JITT_DLL_HF (at high frequencies) or
CLKIN_PER_JITT_DLL_LF (at low frequencies). Larger jitter (period changes) can cause
the DCM to lose lock, indicated by the LOCKED output deasserting. The user must then
reset the DCM. The cycle-to-cycle input jitter must be kept to less than
CLKIN_CYC_JITT_DLL_LF in the low frequencies and CLKIN_CYC_JITT_DLL_HF for
the high frequencies.
Changing the period of the input clock beyond the maximum input period jitter
specification requires a manual reset of the DCM. Failure to reset the DCM produces an
unreliable LOCKED signal and output clock. It is possible to temporarily stop the input
clock and feedback clock with little impact to the deskew circuit, as long as CLKFX or
CLKFX180 is not used.
If the input clock is stopped and CLKFX or CLKFX180 is used, the CLKFX or CLKFX180
outputs might stop toggling, and DO[2] (CLKFX stopped) is asserted. The DCM must be
reset to recover from this event.
The DO[2] CLKFX stopped status is asserted 100 µs after CLKFX is stopped. CLKFX does
not resume and DO[2] does not deassert until the DCM is reset.
In any other case, the clock should not be stopped for more than 100 ms to minimize the
effect of device cooling; otherwise, the tap delays might change. The clock should be
stopped during a Low or a High phase, and must be restored with the same input clock
period/frequency. During this time, LOCKED stays High and remains High when the
clock is restored. Thus, a High on LOCKED does not necessarily mean that a valid clock is
available.
When stopping the input clock (CLKIN remains High or Low for one or more clock cycles),
one to nine more output clock cycles are still generated as the delay line is flushed. When
the output clock stops, the CLKIN stopped (DO[1]) signal is asserted. When the clock is
restarted, the output clock cycles are not generated for one to eight clocks while the delay
line is filled. The most common case is two or three clocks. The DO[1] signal is deasserted
once the output clock is generated. CLKIN can be restarted with any phase relationship to
the previous clock. If the frequency has changed, the DCM requires a reset. The DO[1] is
forced Low whenever LOCKED is Low. When the DCM is in the locking process, DO[1]
status is held Low until LOCKED is achieved.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010