XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 95

• Manufacturer Part Number: XC5VLX50T-2FFG665I
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
PLL Programming
Phase Shift
Determine the Input Frequency
In many cases, there needs to be a phase shift between clocks. The phase shift resolution in
time units is defined as: PS = 1/8 F
shifted clocks at 45° each.
The higher the VCO frequency, the smaller the phase shift resolution. Since the VCO has a
distinct operating range, it is possible to bound the phase shift resolution using from
1/8 F
Each output counter is individually programmable allowing each counter to have a
different phase shift based on the output frequency of the VCO.
Note:
duty cycle and 0 value. Consult the architecture wizard for other phase-shift settings.
Programming of the PLL must follow a set flow to ensure configuration that guarantees
stability and performance. This section describes how to program the PLL based on certain
design requirements. A design can be implement in two ways, directly through the GUI
interface (the PLL Wizard) or directly implementing the PLL through instantiation.
Regardless of the method selected, the following information is necessary to program the
PLL:
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The first step is to determine the input frequency. This allows all possible output
frequencies to be determined by using the minimum and maximum input frequencies to
define the D counter range, the VCO operating range to determine the M counter range,
and the output counter range since it has no restrictions. There can be a very large number
of frequencies. In the worst case, there will be 52 x 64 x 128 = 425,984 possible
combinations. In reality, the total number of different frequencies is less since the entire
range of the M and D counters cannot be realized and there is overlap between the various
settings. As an example, consider F
20 MHz, then D can only go from 1 to 5. For D = 1, M can only have values from four to 11.
If D = 2, M can have values from 8 to 22. In addition, D = 1 M = 4 is a subset of D = 2 M = 8
allowing the D = 1 M = 4 case to be dropped. For this case, only D = 3, 4, 5, and 7 are
considered since all other D values are subsets of these cases.
This drastically reduces the number of possible output frequencies. The output frequencies
are sequentially selected. The desired output frequency should be checked against the
possible output frequencies generated. Once the first output frequency is determined, an
additional constraint can be imposed on the values of M and D. This can further limit the
Reference clock period
Output clock frequencies (up to six maximum)
Output clock duty cycle (default is 50%)
Output clock phase shift relative in number of clock cycles relative to the fastest
output clock.
Desired bandwidth of the PLL (default is OPTIMIZED and the bandwidth is chosen
in software)
Compensation mode (automatically determined by the software)
Reference clock jitter in UI (i.e., a percentage of the reference clock period)
VCO_MIN
Phase shifts other than 45° are possible. A finer phase shift resolution depends on the output
to 1/8 F
VCO_MAX
www.xilinx.com
.
VCO
IN
= 100 MHz. If the minimum PFD frequency is
or D/8MF
IN
since the VCO can provide eight phase
General Usage Description
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