XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 20

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Part Number:
XC5VLX50T-2FFG665I
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Part Number:
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Table 39: GTX_DUAL Tile Quiescent Supply Current
GTX_DUAL Tile DC Input and Output Levels
Table 40
ended output voltage swing.
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details.
Table 40: GTX_DUAL Tile DC Specifications
X-Ref Target - Figure 6
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
4.
I
I
I
AVCCPLLQ
Symbol
AVTTRXQ
AVTTTXQ
I
DV
The output swing and preemphasis levels are programmable using the attributes discussed in UG198:Virtex-5 FPGA RocketIO GTX
Transceiver User Guide and can result in values lower than reported in this table.
Values outside of this range can be used as appropriate to conform to specific protocols and standards.
Typical values are specified at nominal voltage, 25°C.
Device powered and unconfigured.
Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
GTX_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTX_DUAL tiles in the target TXT or FXT device.
Symbol
AVCCQ
V
T
V
DV
+V
V
R
OSKEW
C
CMOUT
SEOUT
V
R
0
CMIN
PPOUT
OUT
EXT
PPIN
IN
IN
summarizes the DC output specifications of the GTX_DUAL tiles in Virtex-5 FPGAs.
P
N
Quiescent MGTAVTTTX (transmitter termination) supply current
Quiescent MGTAVCCPLL (PLL) supply current
Quiescent MGTAVTTRX (receiver termination) supply current. Includes
MGTAVTTRXCQ.
Quiescent MGTAVCC (analog) supply current
Differential peak-to-peak input
voltage
Absolute input voltage
Common mode input voltage
Differential peak-to-peak output
voltage
Single-ended output voltage
swing
Common mode output voltage
Differential input resistance
Differential output resistance
Transmitter output skew
Recommended external AC coupling capacitor
(1)
(1)
DC Parameter
Figure 7
Figure 6: Single-Ended Output Voltage Swing
shows the peak-to-peak differential output voltage.
External AC coupled ≤ 4.25 Gb/s
External AC coupled > 4.25 Gb/s
DC coupled
MGTAVTTRX = 1.2V
DC coupled
MGTAVTTRX = 1.2V
TXBUFDIFFCTRL = 111
TXBUFDIFFCTRL = 111
Equation based
MGTAVTTTX = 1.2V
Description
www.xilinx.com
Conditions
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(2)
–400
Min
125
125
85
85
75
1200 – DV
Typ
800
100
100
100
2
Figure 6
Typ
8.2
0.8
1.2
9.0
MGTAVTTRX +400
PPOUT
(1)
up to 1320
shows the single-
1800
1800
1400
Max
/2
700
120
120
200
8
Max
21.6
12.0
50.4
4.8
ds202_01_051607
V
SEOUT
Units
mA
mA
mA
mA
Units
mV
mV
mV
mV
mV
mV
mV
nF
ps
Ω
Ω
20

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