XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 38

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4” of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4” trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in
X-Ref Target - Figure 11
Table 59: Output Delay Measurement Methodology
DS202 (v5.3) May 5, 2010
Product Specification
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
FPGA Output
Figure 11: Single Ended Test Setup
Description
V
REF
R
C
(probe capacitance)
REF
REF
Figure 11
V
(voltage level when taking
delay measurement)
MEAS
DS202_06_111608
and
Figure
www.xilinx.com
12.
LVCMOS33
LVTTL (all)
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 12
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
I/O Standard
Attribute
test setup, using values from
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
decrease in delay yields the actual propagation delay of
the PCB trace.
FPGA Output
Figure 12: Differential Test Setup
REF
, R
REF
, C
C
MEAS
MEAS
REF
R
REF
(Ω)
1M
1M
1M
1M
1M
1M
25
25
25
25
25
25
25
25
50
25
50
REF
.
.
, and V
Table
C
(pF)
10
10
10
10
10
10
REF
0
0
0
0
0
0
0
0
0
0
0
(2)
(2)
(2)
(2)
(3)
(3)
MEAS
(1)
59.
R
fully describe
REF
V
V
V
ds202_12_042808
1.65
1.25
0.75
0.94
2.03
0.94
2.03
0.94
2.03
MEAS
(V)
0.8
1.4
0.9
0.6
1.0
0.9
REF
REF
V
MEAS
+
V
0.75
0.75
(V)
3.3
3.3
3.3
1.2
1.5
1.5
REF
0
0
0
0
0
0
0
0
38

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