XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 46

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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Manufacturer
Quantity
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Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
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Quantity:
10 000
Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
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CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 66: CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 67: CLB Shift Register Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
Sequential Delays
T
T
Setup and Hold Times Before/After Clock CLK
T
T
T
T
Clock CLK
T
T
Sequential Delays
T
T
T
Setup and Hold Times Before/After Clock CLK
T
T
T
Clock CLK
T
AS
SHCKO
SHCKO_1
DS
WS
CECK
MPW
MCP
REG
REG_MUX
REG_M31
WS
CECK
DS
MPW
/T
/T
/T
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
/T
/T
AH
DH
DH
WH
/T
WH
/T
Symbol
Symbol
CKCE
CKCE
Clock to A – B outputs
Clock to AMUX – BMUX outputs
A – D inputs to CLK
Address An inputs to clock
WE input to clock
CE input to CLK
Minimum pulse width
Minimum clock period
Clock to A – D outputs
Clock to AMUX – DMUX output
Clock to DMUX output via M31 output
WE input
CE input to CLK
A – D inputs to CLK
Minimum pulse width
Description
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
–0.06
–0.08
1.08
1.19
0.72
0.20
0.41
0.20
0.34
0.36
0.70
1.40
-3
–0.06
–0.08
1.23
1.33
0.99
0.21
0.23
0.57
0.07
0.60
-3
Speed Grade
–0.04
–0.07
Speed Grade
1.26
1.38
0.84
0.22
0.46
0.22
0.39
0.42
0.82
1.64
-2
–0.04
–0.07
1.43
1.55
1.15
0.24
0.27
0.66
0.09
0.70
-2
–0.02
–0.06
1.54
1.68
1.03
0.26
0.54
0.27
0.46
0.51
1.00
2.00
-1
–0.02
–0.06
1.73
1.87
1.38
0.29
0.33
0.78
0.11
0.85
-1
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
ns, Min
ns, Min
ns, Min
ns, Min
Units
Max
Max
Max
ns,
ns,
ns,
46

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