XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 60

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
XILINX
0
Company:
Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
XILINX
Quantity:
270
Output Clock Jitter
Table 79: Output Clock Jitter
Output Clock Phase Alignment
Table 80: Output Clock Phase Alignment
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Notes:
1.
2.
3.
4.
Clock Synthesis Period Jitter
T
T
T
T
T
T
T
T
Phase Offset Between CLKIN and CLKFB
T
Phase Offset Between Any DCM Outputs
T
T
T
Duty Cycle Precision
T
T
PERJITT_0
PERJITT_90
PERJITT_180
PERJITT_270
PERJITT_2X
PERJITT_DV1
PERJITT_DV2
PERJITT_FX
IN_FB_OFFSET
OUT_OFFSET_1X
OUT_OFFSET_2X
OUT_OFFSET_FX
DUTY_CYC_DLL
DUTY_CYC_FX
Values for this parameter are available in the Architecture Wizard.
All phase offsets are in respect to group CLK1X.
CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE. The duty cycle distortion includes the global clock tree (BUFG).
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Symbol
Symbol
(2)
CLKIN/CLKFB
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180, CLKDV
CLKFX, CLKFX180
DLL outputs
DFS outputs
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
(1)
(3)
Description
(4)
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Constraints
Constraints
±140
±150
±160
±150
±150
Note 1
±50
±120
±120
±120
±120
±200
±150
±300
-3
-3
Speed Grade
Speed Grade
Note 1
±140
±150
±160
±150
±150
±120
±120
±120
±120
±200
±150
±300
±50
-2
-2
Note 1
±160
±180
±180
±120
±120
±120
±120
±230
±180
±345
±200
±220
±60
-1
-1
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
60

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