XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 61

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
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Quantity:
10 000
Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
XILINX
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XC5VLX50T-2FFG665I
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Quantity:
270
Table 81: Miscellaneous Timing Parameters
Table 82: Frequency Synthesis
Table 83: DCM Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
Time Required to Achieve LOCK
T
T
T
T
T
T
T
T
T
T
T
Fine Phase Shifting
T
T
Delay Lines
T
T
T
T
CLKFX_MULTIPLY
CLKFX_DIVIDE
T
T
T
DLL_240
DLL_120_240
DLL_60_120
DLL_50_60
DLL_40_50
DLL_30_40
DLL_24_30
DLL_30
FX_MIN
FX_MAX
DLL_FINE_SHIFT
RANGE_MS
RANGE_MR
TAP_MS_MIN
TAP_MS_MAX
TAP_MR_MIN
TAP_MR_MAX
DMCCK_PSEN
DMCCK_PSINCDEC
DMCKO_PSDONE
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Symbol
/ T
DMCKC_PSEN
/ T
Symbol
DMCKC_PSINCDEC
Attribute
DLL output – Frequency range > 240 MHz
DLL output – Frequency range 120 - 240 MHz
DLL output – Frequency range 60 - 120 MHz
DLL output – Frequency range 50 - 60 MHz
DLL output – Frequency range 40 - 50 MHz
DLL output – Frequency range 30 - 40 MHz
DLL output – Frequency range 24 - 30 MHz
DLL output – Frequency range < 30 MHz
DFS outputs
Multiplication factor for DLL lock time with Fine Shift
Absolute shifting range in maximum speed mode
Absolute shifting range in maximum range mode
Tap delay resolution (Min) in maximum speed mode
Tap delay resolution (Max) in maximum speed mode
Tap delay resolution (Min) in maximum range mode
Tap delay resolution (Max) in maximum range mode
(2)
PSEN Setup/Hold
PSINCDEC Setup/Hold
Clock to out of PSDONE
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Min
2
1
1300.00
2000.00
3600.00
5000.00
5000.00
1.20
0.00
1.20
0.00
1.00
250.00
900.00
80.00
10.00
10.00
10.00
30.00
10.00
40.00
-3
2.00
7.00
7.00
-3
Speed Grade
Speed Grade
1300.00
2000.00
3600.00
5000.00
5000.00
250.00
900.00
1.35
0.00
1.35
0.00
1.12
30.00
40.00
80.00
10.00
10.00
10.00
10.00
2.00
7.00
7.00
-2
-2
Max
1300.00
2000.00
3600.00
5000.00
5000.00
33
32
250.00
900.00
80.00
10.00
10.00
10.00
30.00
10.00
40.00
1.56
0.00
1.56
0.00
1.30
2.00
7.00
7.00
-1
-1
Units
Units
ms
ms
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ps
ps
ps
ps
61

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