XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 35

IC FPGA VIRTEX-4 FX 60K 1152FBGA

XC4VFX60-10FFG1152C

Manufacturer Part Number
XC4VFX60-10FFG1152C
Description
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

Total Ram Bits
4276224
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
No. Of Logic Blocks
6656
No. Of Macrocells
56880
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
576
Clock Management
DCM
Core Supply
RoHS Compliant
Package
1152FCBGA
Family Name
Virtex®-4
Device Logic Units
56880
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
576
Ram Bits
4276224
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
XILINX
0
Part Number:
XC4VFX60-10FFG1152C
Quantity:
205
Part Number:
XC4VFX60-10FFG1152C
0
XtremeDSP™ Switching Characteristics
Table 42: XtremeDSP Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Setup and Hold of CE Pins
Setup and Hold Times of Data
Sequential Delays
Combinatorial
Maximum Frequency
T
T
T
T
T
T
T
T
T
F
DSPCCK_CE
DSPCCK_RST
DSPDCK_{AA, BB, CC}
DSPCKD_{AA, BB, CC}
DSPDCK_{AM, BM}
DSPCKD_{AM, BM}
DSPCKO_PP
DSPCKO_PM
DSPDO_{AP, BP}L
MAX
Symbol
/
T
/
T
DSPCKC_CE
DSPCKC_RST
/
/
Setup/Hold of all CE inputs of the DSP48 slice
Setup/Hold of all RST inputs of the DSP48 slice
Setup/Hold of {A, B, C} input to {A, B, C} register
Setup/Hold of {A, B} input to M register
Clock to out from P register to P output
Clock to out from M register to P output
{A, B} input to P output
(LEGACY_MODE = MULT18X18)
From {A, B} register to P register
(LEGACY_MODE = MULT18X18)
Fully Pipelined
Description
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
317.46
500.00
0.39
0.09
0.32
0.09
0.25
0.23
1.82
0.00
0.64
2.38
3.53
-12
Speed Grade
285.71
450.05
0.43
0.10
0.36
0.10
0.28
0.26
2.03
0.00
0.71
2.65
3.92
-11
253.94
400.00
0.49
0.12
0.40
0.12
0.32
0.29
2.28
0.00
0.79
2.98
4.41
-10
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
35

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