XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 39

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued)
Table 46: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
Notes:
1.
2.
3.
4.
5.
6.
Input Clocks (High Frequency Mode)
Outputs Clocks (Low Frequency Mode)
CLKOUT_FREQ_FX_LF_MR_MAX
Input Clocks (Low Frequency Mode)
CLKOUT_FREQ_FX_HF_MS_MIN
CLKOUT_FREQ_FX_HF_MS_MAX
CLKIN_FREQ_DLL_HF_MS_MIN
CLKIN_FREQ_DLL_HF_MS_MAX
CLKIN_FREQ_FX_HF_MS_MIN
CLKIN_FREQ_FX_HF_MS_MAX
PSCLK_FREQ_HF_MS_MIN
PSCLK_FREQ_HF_MS_MAX
CLKOUT_FREQ_1X_LF_MR_MIN
CLKOUT_FREQ_1X_LF_MR_MAX
CLKOUT_FREQ_2X_LF_MR_MIN
CLKOUT_FREQ_2X_LF_MR_MAX
CLKOUT_FREQ_DV_LF_MR_MIN
CLKOUT_FREQ_DV_LF_MR_MAX
CLKOUT_FREQ_FX_LF_MR_MIN
CLKIN_FREQ_DLL_LF_MR_MIN
CLKIN_FREQ_DLL_LF_MR_MAX
CLKIN_FREQ_FX_LF_MR_MIN
CLKIN_FREQ_FX_LF_MR_MAX
PSCLK_FREQ_LF_MR_MIN
PSCLK_FREQ_LF_MR_MAX
DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to
55/45).
The DCM must be reset if the clock input clock stops for more than 100 ms.
These values also apply when using both DLL and DFS outputs.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to
55/45).
The DCM must be reset if the clock input clock stops for more than 100 ms.
These values also apply when using both DLL and DFS outputs.
Symbol
Symbol
(6)
(6)
CLKFX, CLKFX180
CLKIN (using DLL outputs only)
CLKIN (using DFS outputs)
PSCLK
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
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Description
Description
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(1,3,4,5,6)
(2,3,4)
(1,3,4,5)
(2,3,4)
262.50
26.7
-12
210
350
150
500
350
500
-12
1.2
50
19
40
38
80
19
40
19
40
35
1
1
1
Speed Grade
Speed Grade
236.30
-11
210
315
150
450
315
450
-11
1.2
50
19
36
38
72
24
19
36
19
36
32
1
1
1
210.00
21.3
210
300
150
400
300
400
-10
-10
1.2
50
19
32
38
64
19
32
19
32
28
1
1
1
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
KHz
39