XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 41

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Clock Jitter
Table 48: Output Clock Jitter
Output Clock Phase Alignment
Table 49: Output Clock Phase Alignment
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
4.
Clock Synthesis Period Jitter
Phase Offset Between CLKIN and CLKFB
Phase Offset Between Any DCM Outputs
Duty Cycle Precision
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
CLKIN
All CLK outputs
DLL outputs
DFS outputs
PMCD outputs are not included in this table because they do not introduce jitter.
Values for this parameter are available from the architecture wizard.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION=TRUE.
The measured value includes the duty cycle distortion of the global clock tree.
Description
/
CLKFB
Description
(1)
(2)
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
CLKOUT_DUTY_CYCLE_DLL
CLKOUT_DUTY_CYCLE_FX
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_FX
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
Symbol
Symbol
www.xilinx.com
(4)
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(3,4)
Constraints
Constraints
Note (2)
±100
±150
±150
±150
±200
±150
±300
±120
±140
±150
±200
-12
-12
Speed Grade
Speed Grade
Note (2)
±200
±150
±300
±100
±150
±150
±150
±120
±140
±150
±200
-11
-11
Note (2)
±100
±150
±150
±150
±200
±150
±300
±120
±140
±150
±200
-10
-10
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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