XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 47

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part Number
XC5VSX50T-2FF665C
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Block RAM and FIFO Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Block RAM and FIFO Clock to Out Delays
T
T
T
T
T
Setup and Hold Times Before/After Clock CLK
T
T
T
T
T
T
T
T
RCKO_DO
RCKO_FLAGS
RCKO_POINTERS
RCKO_ECCR
RCKO_ECC
RCCK_ADDR
RDCK_DI
RDCK_DI_ECC
RCCK_EN
RCCK_REGCE
RCCK_SSR
RCCK_WE
RCCK_WREN
/T
/T
/T
and T
RCKD_DI
/T
RCKC_EN
Symbol
RCKC_WE
/T
/T
RCKC_SSR
/T
/T
RCKC_ADDR
RCKC_WREN
RCKC_REGCE
RCKD_DI_ECC
RCKO_DOR
(1)
Clock CLK to DOUT output (without output
register)
Clock CLK to DOUT output (with output register)
Clock CLK to DOUT output with ECC (without output
register)
Clock CLK to DOUT output with ECC (with output
register)
Clock CLK to DOUT output with Cascade (without
output register)
Clock CLK to DOUT output with Cascade (with output
register)
Clock CLK to FIFO flags outputs
Clock CLK to FIFO pointer outputs
Clock CLK to BITERR (with output register)
Clock CLK to BITERR (without output register)
Clock CLK to ECCPARITY in standard ECC mode
Clock CLK to ECCPARITY in ECC encode only mode
ADDR inputs
DIN inputs
DIN inputs with ECC in standard mode
DIN inputs with ECC encode only
Block RAM Enable (EN) input
CE input of output register
Synchronous Set/ Reset (SSR) input
Write Enable (WE) input
WREN/RDEN FIFO inputs
(2,3)
(2,3)
(4,5)
(4)
(9)
(8)
(2)
Description
www.xilinx.com
(10)
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(6)
(9
(7)
(9)
(4,5)
1.79
0.61
2.64
0.66
2.10
0.91
0.76
1.10
0.66
2.48
1.29
0.77
0.34
0.30
0.27
0.28
0.33
0.32
0.68
0.32
0.32
0.15
0.15
0.22
0.17
0.23
0.44
0.16
0.36
0.30
-3
Speed Grade
1.92
0.69
3.03
0.77
2.44
1.07
0.87
1.26
0.77
2.85
1.47
0.89
0.40
0.32
0.30
0.28
0.37
0.33
0.72
0.33
0.36
0.15
0.16
0.24
0.21
0.25
0.51
0.17
0.41
0.34
-2
0.93
3.41
2.19
0.82
3.61
0.93
2.94
1.30
1.02
1.48
1.74
1.05
0.48
0.36
0.35
0.29
0.42
0.36
0.77
0.36
0.42
0.15
0.18
0.27
0.26
0.28
0.63
0.18
0.48
0.40
-1
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
47

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