XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet

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XCV2000E-8FG1156C

Manufacturer Part Number
XCV2000E-8FG1156C
Description
IC FPGA 1.8V C-TEMP 1156-BGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet

Specifications of XCV2000E-8FG1156C

Number Of Logic Elements/cells
43200
Number Of Labs/clbs
9600
Total Ram Bits
655360
Number Of I /o
804
Number Of Gates
2541952
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1156-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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DS022-1 (v2.3) July 17, 2002
Features
DS022-1 (v2.3) July 17, 2002
Production Product Specification
© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Fast, High-Density 1.8 V FPGA Family
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Highly Flexible SelectI/O+™ Technology
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Differential Signalling Support
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Proprietary High-Performance SelectLink™
Technology
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Sophisticated SelectRAM+™ Memory Hierarchy
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* ZBT is a trademark of Integrated Device Technology, Inc.
Densities from 58 k to 4 M system gates
130 MHz internal performance (four LUT levels)
Designed for low-power operation
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Supports 20 high-performance interface standards
Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
Differential I/O signals can be input, output, or I/O
Compatible with standard differential devices
LVPECL and LVDS clock inputs for 300+ MHz
clocks
Double Data Rate (DDR) to Virtex-E link
Web-based HDL generation methodology
1 Mb of internal configurable distributed RAM
Up to 832 Kb of synchronous internal block RAM
True Dual-Port BlockRAM capability
Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
Designed for high-performance Interfaces to
External Memories
200 MHz ZBT* SRAMs
200 Mb/s DDR SDRAMs
Supported by free Synthesizable reference design
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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www.xilinx.com
1-800-255-7778
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Virtex™-E 1.8 V
Field Programmable Gate Arrays
Production Product Specification
High-Performance Built-In Clock Management Circuitry
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Flexible Architecture Balances Speed and Density
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Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
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SRAM-Based In-System Configuration
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Advanced Packaging Options
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0.18 μm 6-Layer Metal Process
100% Factory Tested
Eight fully digital Delay-Locked Loops (DLLs)
Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
Clock Multiply and Divide
Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input function
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
Further compile time reduction of 50%
Internet Team Design (ITD) tool ideal for
million-plus gate density designs
Wide selection of PC and workstation platforms
Unlimited re-programmability
0.8 mm Chip-scale
1.0 mm BGA
1.27 mm BGA
HQ/PQ
Module 1 of 4
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XCV2000E-8FG1156C Summary of contents

Page 1

R DS022-1 (v2.3) July 17, 2002 Features • Fast, High-Density 1.8 V FPGA Family - Densities from system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant ...

Page 2

... XCV400E 569,952 129,600 XCV600E 985,882 186,624 XCV1000E 1,569,178 331,776 XCV1600E 2,188,742 419,904 XCV2000E 2,541,952 518,400 XCV2600E 3,263,755 685,584 XCV3200E 4,074,387 876,096 Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source ...

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R resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be ...

Page 4

Virtex™-E 1.8 V Field Programmable Gate Arrays Virtex-E Ordering Information Example: XCV300E-6PQ240C Device Type Speed Grade (-6, -7, -8) Revision History The following table shows the revision history for this document. Date Version 12/7/99 1.0 Initial Xilinx release. 1/10/00 1.1 ...

Page 5

... Revised footnote for Table 14. 2/12/01 1.9 • Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and XCV2000E devices. • Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. • Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package. • ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS022-1 (v2.3) July 17, 2002 Production Product Specification ...

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R DS022-2 (v2.8) January 16, 2006 Architectural Description Virtex-E Array The Virtex-E user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for ...

Page 8

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 1: Supported I/O Standards I/O Output Input Standard V V CCO CCO LVTTL 3.3 3.3 LVCMOS2 2.5 2.5 LVCMOS18 1.8 1.8 SSTL3 I & II 3.3 N/A SSTL2 I & II 2.5 ...

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R Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure multiple V pins, all of which must be connected to the CCO same voltage. This voltage is determined by the output ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays G4 G3 LUT LUT F5IN CLK CE Storage Elements The storage elements in the ...

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... XCV200E XCV300E XCV400E XCV600E XCV1000E Dedicated Routing. XCV1600E XCV2000E XCV2600E XCV3200E As illustrated in fully synchronous dual-ported (True Dual Port) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured indepen- dently, providing built-in bus-width conversion. ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays RAMB4_S#_S# WEA ENA DOA[#:0] RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0] Figure 6: Dual-Port Block SelectRAM Table 5 shows the depth and width aspect ratios for the block SelectRAM. ...

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R Dedicated Routing Some classes of signal require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedi- cated routing resources are provided for two classes of signal. • Horizontal routing resources are provided for on-chip 3-state buses. Four ...

Page 14

Virtex™-E 1.8 V Field Programmable Gate Arrays The DLL also operates as a clock mirror. By driving the out- put from a DLL off-chip and then back on again, the DLL can be used to deskew a board level clock ...

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R IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI Instruction Set The Virtex-E series Boundary Scan instruction set also includes instructions to configure the device and read back configuration data (CFG_IN, CFG_OUT, and JSTART). ...

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... XCV100E XCV200E Figure 12. XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E Note: Attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Including Boundary Scan in a Design 990602001 Since the Boundary Scan pins are dedicated, no special element needs to be added to the design unless an internal data register (USER1 or USER2) is desired ...

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R Development System Virtex-E FPGAs are supported by the Xilinx Foundation and Alliance Series CAE tools. The basic methodology for Virtex-E design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays For in-circuit debugging, an optional download and read- back cable is available. This cable connects the FPGA in the target system workstation. After downloading the design into the FPGA, ...

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... XCV300E 1, 875,648 XCV400E 2,693,440 XCV600E 3,961,632 XCV1000E 6,587,520 XCV1600E 8,308,992 XCV2000E 10,159,648 XCV2600E 12,922,336 XCV3200E 16,283,712 Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data. The serial bitstream must be set up at the DIN input pin a short time before each rising edge of an externally generated CCLK ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays . Optional Pull-up 1 Resistor on Done PROGRAM Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to ...

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R Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases Release INIT INIT when finished. INIT? Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance instead ...

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R Apply Power FPGA starts to clear configuration memory. PROGRAM from Low to High FPGA makes a final clearing pass and releases INIT when finished. Release INIT INIT? Set WRITE = Low Enter Data Source Set CS = Low Apply ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Configuration through the TAP uses the CFG_IN instruc- tion. This instruction allows data input on TDI to be con- verted into data packets for the internal configuration bus. The following steps are required ...

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R the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addi- tion, the GTS, GSR, and GWE events can be made depen- ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays CLKDLL CLKIN CLK0 CLK90 CLKFB CLK180 CLK270 CLK2X CLKDV RST LOCKED Figure 22: Standard DLL Symbol CLKDLL CLKDLLHF CLKIN CLK0 CLKFB CLK180 CLKDV RST LOCKED ds022_027_121099 Figure 23: High Frequency DLL Symbol CLKDLLHF ...

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R ground. As the DLL delay taps reset to zero, glitches can occur on the DLL clock output pins. Activation of the RST pin can also severely affect the duty cycle of the clock out- put pins. Furthermore, the DLL ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays DLL Properties Properties provide access to some of the Virtex-E series DLL features, (for example, clock division and duty cycle correction). Duty Cycle Correction Property The 1x clock outputs, CLK0, CLK90, CLK180, and ...

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R Useful Application Examples The Virtex-E DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. The Verilog and VHDL example files are available at: ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip Standard Usage ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Because any single DLL can access only two BUFGs at most, any additional output clock signals must be routed from the DLL in this example on the high speed backbone routing. The dll_2x ...

Page 31

R RAMB4_S#_S# WEA ENA DOA[#:0] RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0] Figure 31: Dual-Port Block SelectRAM+ Memory RAMB4_S RST DO[#:0] CLK ADDR[#:0] DI[#:0] ds022_033_121399 Figure 32: Single-Port Block SelectRAM+ Memory Table 14: Available ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Data Output Bus—DO[A|B]<#:0> The data out bus reflects the contents of the memory cells referenced by the address bus at the last active clock edge. During a write operation, the data out bus ...

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R indicating that the block SelectRAM+ memory is now dis- abled. The DO bus retains the last value. Dual Port Timing Figure 34 shows a timing diagram for a true dual-port read/write block SelectRAM+ memory. The clock on port A ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays CLK_A ADDR_A EN_A WE_A DI_A DO_A CLK_B ADDR_B 00 EN_B WE_B DI_B 1111 DO_B MEM (00) Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory At the third rising edge ...

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R Initialization in Verilog and Synopsys The block SelectRAM+ structures can be initialized in Verilog for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the Verilog code uses a def- param to pass the ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays VHDL Initialization Example library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE ...

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R Verilog Initialization Example module MYMEM (CLK, WE, ADDR, DIN, DOUT); input CLK, WE; input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string //set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Fundamentals Modern bus applications, pioneered by the largest and most influential companies in the digital electronics industry, are commonly introduced with a new I/O standard tailored spe- cifically to the needs of that ...

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R standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. SSTL3 — Stub Series Terminated Logic for 3.3V The Stub Series Terminated Logic for 3.3V, or SSTL3 stan- dard is a general purpose 3.3V memory bus standard ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays The voltage reference signal is “banked” within the Virtex-E device on a half-edge basis such that for all packages there are eight independent V banks internally. See REF for a representation of the ...

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R represents a combination of the LVTTL IBUFG and BUFG symbols, such that the output of the BUFGP can connect directly to the clock pins throughout the design. Unlike previous architectures, the Virtex-E BUFGP symbol can only be placed in ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays LVTTL 3-state output buffers have selectable drive strengths. The format for LVTTL OBUFT symbol names is as follows: OBUFT_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast (Slow), and <drive_strength> is specified in ...

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R IOBUF x133_06_111699 Figure 42: Input/Output Buffer Symbol (IOBUF) The following list details variations of the IOBUF symbol. • IOBUF • IOBUF_S_2 • IOBUF_S_4 • IOBUF_S_6 • IOBUF_S_8 • IOBUF_S_12 • IOBUF_S_16 • IOBUF_S_24 • IOBUF_F_2 ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Flip-Flop/Latch Property The Virtex-E series I/O Block (IOB) includes an optional register on the input path, an optional register on the output path, and an optional register on the 3-state control pin. ...

Page 45

R Input termination techniques include the following. • None • Parallel (Shunt) These termination techniques can be applied in any combi- nation. A generic example of each combination of termina- tion methods appears in Figure 43. Unterminated Double Parallel Terminated ...

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... HSTL Class III HSTL Class IV SSTL2 Class I SSTL2 Class II SSTL3 Class I SSTL3 Class II CTT AGP Note: This analysis assumes load for each output. Table 22: Virtex-E Equivalent Power/Ground Pairs Pkg/Part XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E CS144 12 PQ240 20 HQ240 BG352 20 BG432 BG560 (1) ...

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R Application Examples Creating a design with the SelectI/O features requires the instantiation of the desired library symbol within the design code. At the board level, designers need to know the termi- nation techniques required for each I/O standard. This ...

Page 48

Virtex™-E 1.8 V Field Programmable Gate Arrays HSTL A sample circuit illustrating a valid termination technique for HSTL_I appears in Figure 46. A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 47. Table 25: HSTL Class ...

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R SSTL3_I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 49. DC voltage specifications appear in Table 28. SSTL3 Class 3.3V CCO 50Ω 25Ω 1.5V ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays SSTL2_II A sample circuit illustrating a valid termination technique for SSTL2_II appears in Figure 52. DC voltage specifications appear in Table 31. SSTL2 Class 1.25V 2.5V CCO ...

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R LVTTL LVTTL requires no termination. DC voltage specifications appears in Table 34. Table 34: LVTTL Voltage Specifications Parameter Min V 3.0 CCO V - REF 2.0 IH −0 2 ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays LVDS Depending on whether the device is transmitting an LVDS signal or receiving an LVDS signal, there are two different circuits used for LVDS termination. A sample circuit illustrat- ing a valid termination ...

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R Termination Resistor Packs Resistor packs are available with the values and the config- uration required for LVDS and LVPECL termination from Bourns, Inc., as listed in Table. For pricing and availability, please contact Bourns directly at http://www.bourns.com Table 40: ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Optional N-side Some designers might prefer to also instantiate the N-side buffer for the global clock buffer. This allows the top-level net list to include net connections for both PCB layout and sys- ...

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R Table 42: Input Library Macros Name Inputs IBUFDS_FD_LVDS I, IB, C IBUFDS_FDE_LVDS I, IB, CE, C IBUFDS_FDC_LVDS I, IB, C, CLR IBUFDS_FDCE_LVDS I, IB, CE, C, CLR IBUFDS_FDP_LVDS I, IB, C, PRE IBUFDS_FDPE_LVDS I, IB, CE, C, PRE IBUFDS_FDR_LVDS ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Table 43: Output Library Macros Name Inputs OBUFDS_FD_LVDS D, C OBUFDS_FDE_LVDS DD, CE, C OBUFDS_FDC_LVDS D, C, CLR OBUFDS_FDCE_LVDS D, CE, C, CLR OBUFDS_FDP_LVDS D, C, PRE OBUFDS_FDPE_LVDS D, CE, C, PRE OBUFDS_FDR_LVDS ...

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R The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the “map -pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b” is both inputs ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Table 44: Bidirectional I/O Library Macros Name IOBUFDS_FD_LVDS IOBUFDS_FDE_LVDS IOBUFDS_FDC_LVDS IOBUFDS_FDCE_LVDS IOBUFDS_FDP_LVDS IOBUFDS_FDPE_LVDS IOBUFDS_FDR_LVDS IOBUFDS_FDRE_LVDS IOBUFDS_FDS_LVDS IOBUFDS_FDSE_LVDS IOBUFDS_LD_LVDS IOBUFDS_LDE_LVDS IOBUFDS_LDC_LVDS IOBUFDS_LDCE_LVDS IOBUFDS_LDP_LVDS IOBUFDS_LDPE_LVDS Revision History The following table shows the revision history for ...

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... Changed GCLK0 to BA22 for FG860 package in Table 46. Revised footnote for Table 14. Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and XCV2000E devices. Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Virtex-E Data Sheet The Virtex-E Data Sheet contains the following modules: • DS022-1, Virtex-E 1.8V FPGAs: Introduction and Ordering Information (Module 1) • DS022-2, Virtex-E 1.8V FPGAs: Functional Description (Module 2) Module 2 ...

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... Table 1: Virtex-E Device Speed Grade Designations Speed Grade Designations Device Advance XCV50E XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E All specifications are subject to change without notice. www.xilinx.com 1-800-255-7778 Preliminary Production –8, –7, –6 –8, –7, –6 –8, –7, –6 –8, –7, –6 – ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays DC Characteristics Absolute Maximum Ratings Symbol V Internal Supply voltage relative to GND CCINT V Supply voltage relative to GND CCO V Input Reference Voltage REF (3) V Input voltage relative to GND ...

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... XCV1600E 500 mA XCV2000E 500 mA XCV2600E 500 mA XCV3200E 500 mA XCV50E 2 mA XCV100E 2 mA XCV200E 2 mA XCV300E 2 mA XCV400E 2 mA XCV600E 2 mA XCV1000E 2 mA XCV1600E 2 mA XCV2000E 2 mA XCV2600E 2 mA XCV3200E 2 mA μA All –10 +10 All 8 pF All Note 2 0.25 mA Note 2 0.25 mA Module ...

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... For more details on power supply requirements, see XAPP158 on www.xilinx.com. Product (Commercial Grade) XCV50E - XCV600E XCV812E - XCV2000E XCV2600E - XCV3200E Virtex-E Family, Industrial Grade Notes: 1. Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and lasts for less than 3 ms ...

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Input/Output Standard V, Min V, Max CTT – 0.5 V REF AGP – 0.5 V REF Notes and V for lower drive currents are sample tested Tested according to the relevant specifications. ...

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... IOPLI T XCV50E 1.31 IOPLID XCV100E 1.31 XCV200E 1.39 XCV300E 1.39 XCV400E 1.43 XCV600E 1.55 XCV1000E 1.55 XCV1600E 1.59 XCV2000E 1.59 XCV2600E 1.59 XCV3200E 1.59 www.xilinx.com 1-800-255-7778 2. For other standards, adjust the delays with the 8. (1) Speed Grade - 0.8 0.8 0.8 1.0 1 ...

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... 0.18 IOCKIQ T / IOPICK All 0. IOICKP T / XCV50E 1. IOPICKD T IOICKPD XCV100E 1. XCV200E 1. XCV300E 1. XCV400E 1. XCV600E 1. XCV1000E 1. XCV1600E 1. XCV2000E 1. XCV2600E 1. XCV3200E 1. All 0.28 / IOICECK T 0.0 IOCKICE T All 0.38 IOSRCKI T All 0.54 IOSRIQ T All 3.88 GSRQ Table www.xilinx.com 1-800-255-7778 (1) Speed Grade - 1.2 1.3 1.4 1 ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments Notes: 1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see ...

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R IOB Output Switching Characteristics, Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in (2) Description Propagation Delays O input ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values ...

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R Calculation Function of Capacitance ioop T is the propagation delay from the O Input of the IOB to ioop the pad. The values for T are based on the standard ioop capacitive load (C ) ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays Clock Distribution Switching Characteristics Description GCLK IOB and Buffer Global Clock PAD to output. Global Clock Buffer I input to O output I/O Standard Global Clock Input Adjustments Description Data Input Delay Adjustments ...

Page 73

R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used, see worst-case. Precise values are provided by the timing analyzer. Description Combinatorial Delays 4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs ...

Page 74

Virtex™-E 1.8 V Field Programmable Gate Arrays F5IN CLK CE Module COUT LUT ...

Page 75

R CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Description Combinatorial Delays F operand inputs to X ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays CLB Distributed RAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode Shift-Register Mode Clock ...

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R Block RAM Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times before Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low ...

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... DLL output jitter is already included in the timing calculation. Module Symbol Device T XCV50E ICKOFDLL XCV100E IOB XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC www.xilinx.com 1-800-255-7778 (2, 3) Speed Grade Min - Units 1.0 3.1 3 ...

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... Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device T XCV50E ICKOF XCV100E IOB XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC www.xilinx.com 1-800-255-7778 (2) Speed Grade Min - Units 1 ...

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... XCV1000E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV1600E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV2000E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV2600E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV3200E 1.5 / – ...

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... DS022-3 (v2.9.2) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device Min IOB Input Switching XCV50E 1 PSFD PHFD XCV100E 1 XCV200E 1 XCV300E 2 XCV400E 2 XCV600E 2 XCV1000E 2 XCV1600E 2 XCV2000E 2 XCV2600E 2 XCV3200E 2 www.xilinx.com 1-800-255-7778 (2, 3) Speed Grade - Units ...

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Virtex™-E 1.8 V Field Programmable Gate Arrays DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect ...

Page 83

R DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. Description Input Clock Period Tolerance Input Clock Jitter Tolerance ...

Page 84

... Revised footnote for Table 14. 2/12/01 1.9 • Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and XCV2000E devices. • Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. • Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package. • ...

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R Date Version • Under 07/23/01 2.2 • Changes made to SSTL symbol names in Standard Adjustments • Removed T 07/26/01 2.3 • Reworded power supplies footnote to 9/18/01 2.4 • Updated the speed grade designations used in data sheets, ...

Page 86

Virtex™-E 1.8 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS022-3 (v2.9.2) March 14, 2003 Production Product Specification ...

Page 87

R DS022-4 (v2.5) March 14, 2003 Virtex-E Pin Definitions Pin Name Dedicated Pin GCK0, GCK1, Yes GCK2, GCK3 M0, M1, M2 Yes CCLK Yes PROGRAM Yes DONE Yes INIT No BUSY/DOUT No D0/DIN, No D1, D2, D3, D4, D5, D6, ...

Page 88

Virtex™-E 1.8 V Field Programmable Gate Arrays Pinout Differences Between Virtex and Virtex-E Families The same device in the same package for the Virtex-E and Virtex families are pin-compatible with some minor excep- tions, listed in Table 1. XCV200E Device, ...

Page 89

R Low Voltage Differential Signals The Virtex-E family incorporates low-voltage signalling (LVDS and LVPECL). Two pins are utilized for these signals to be connected to a Virtex-E device. These are known as differential pin pairs. Each differential pin pair has ...

Page 90

Virtex™-E 1.8 V Field Programmable Gate Arrays CS144 Chip-Scale Package XCV50E, XCV100E, XCV200E, XCV300E and XCV400E devices in CS144 Chip-scale packages have footprint com- patibility. In the CS144 package, bank pairs that share a side are internally interconnected, permitting four ...

Page 91

R Table 4: CS144 — XCV50E, XCV100E, XCV200E Bank Pin Description 4 IO_L15N_YY 4 IO_L15P_YY 4 IO_L16N_YY 4 IO_VREF_L16P_YY 4 IO_L17N_YY 4 IO_L17P_YY 4 IO_LVDS_DLL_L18P 4 IO_VREF 4 IO_VREF 4 IO_VREF 5 GCK1 IO_LVDS_DLL_L18N 5 IO_L19N_YY 5 ...

Page 92

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 4: CS144 — XCV50E, XCV100E, XCV200E Bank Pin Description 1 VCCO 1 VCCO 2 VCCO 3 VCCO 3 VCCO 4 VCCO 5 VCCO 5 VCCO 6 VCCO 7 VCCO 7 VCCO NA ...

Page 93

R Table 5: CS144 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E P N Pair Bank Pin Pin ...

Page 94

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pin # Pin Description P173 IO_L16N_Y P171 IO_VREF_L17P_Y P170 IO_L17N_Y P169 IO 1 P168 IO_VREF_L18P_Y P167 IO_D1_L18N_Y P163 IO_D2_L19P_YY P162 IO_L19N_YY P161 IO P160 ...

Page 95

R Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pin # Pin Description P74 IO_L43P_YY 1 P73 IO_VREF_L43N_YY P72 IO P71 IO_L44P_YY P70 IO_VREF_L44N_YY P68 IO_L45P_YY P67 IO_L45N_YY 2 P66 IO_VREF_L46P_Y P65 IO_L46N_Y P64 IO_L47P_YY P63 IO_L47N_YY P57 IO_L48N_YY ...

Page 96

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pin # Pin Description P137 VCCINT P104 VCCINT P88 VCCINT P77 VCCINT P43 VCCINT P32 VCCINT P16 VCCINT P240 VCCO P232 VCCO P226 VCCO ...

Page 97

R PQ240 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the pin pair can be used as ...

Page 98

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 7: PQ240 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pair Bank P Pin N Pin 48 6 P56 P57 49 6 P52 P53 50 6 P49 P50 51 6 P46 ...

Page 99

R Table 8: HQ240 — XCV600E, XCV1000E Pin # Pin Description P210 GCK2 P209 IO_LVDS_DLL_L6P P208 IO_VREF P207 VCCO P206 IO_L7N_Y P205 IO_VREF_L7P_Y P204 GND P203 IO_L8N_Y P202 IO_L8P_Y 1 P201 IO_VREF P200 IO_L9N_YY P199 IO_L9P_YY P198 VCCINT P197 VCCO ...

Page 100

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 8: HQ240 — XCV600E, XCV1000E Pin # Pin Description P138 IO_D5_L26N_YY P137 VCCINT P136 VCCO P135 GND P134 IO_D6_L27P_Y P133 IO_VREF_L27N_Y P132 IO_VREF P131 IO_L28P_Y P130 IO_VREF_L28N_Y P129 GND P128 IO_L29P_Y P127 ...

Page 101

R Table 8: HQ240 — XCV600E, XCV1000E Pin # Pin Description P66 IO_VREF_L46P P65 IO_L46N P64 IO_L47P_YY P63 IO_L47N_YY P62 M2 P61 VCCO P60 M0 P59 GND P58 M1 P57 IO_L48N_YY P56 IO_L48P_YY P55 VCCO P54 IO_VREF P53 IO_L49N_Y P52 ...

Page 102

Virtex™-E 1.8 V Field Programmable Gate Arrays HQ240 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the ...

Page 103

R Table 9: HQ240 Differential Pin Pair Summary XCV600E, XCV1000E P N Pair Bank Pin Pin 48 6 P56 P57 49 6 P52 P53 50 6 P49 P50 51 6 P46 P47 52 6 P41 P42 53 6 P38 P39 ...

Page 104

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description IO_LVDS_DLL_L9N 0 GCK3 1 GCK2 1 IO_LVDS_DLL_L9P IO_L10N 1 IO_L10P 1 IO_L11N_Y 1 IO_VREF_1_L11P_Y 1 ...

Page 105

R Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description 2 IO_D3_L30N _Y 2 IO_L31P 2 IO_L31N IO_L32P_YY 2 IO_L32N_YY IO_L33P 3 IO_L33N 3 IO_D4_L34P _Y 3 IO_VREF_3_L34N _Y 3 IO_L35P_YY ...

Page 106

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description 4 IO_VREF_4_L53P_Y 4 IO_L53N_Y 4 IO_L54P 4 IO_L54N IO_LVDS_DLL_L55P 4 GCK0 5 GCK1 5 IO_LVDS_DLL_L55N ...

Page 107

R Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description 6 IO_L74P _Y 6 IO_L75N 6 IO_L75P IO_L76N_YY 7 IO_L76P_YY IO_L77N 7 IO_L77P 7 IO_L78N _Y 7 IO_VREF_7_L78P _Y 7 IO_L79N_YY ...

Page 108

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT 0 VCCO 0 VCCO 0 VCCO 1 VCCO 1 VCCO 1 VCCO 2 ...

Page 109

R BG352 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A check (√) in the AO column indicates that the pin pair can be used ...

Page 110

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 11: BG352 Differential Pin Pair Summary XCV100E, XCV200E, XCV300E P N Pair Bank Pin Pin 55 5 AC13 AD14 56 5 AD15 AC15 57 5 AE16 AE17 58 5 AC16 AF18 59 ...

Page 111

R Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 0 IO_L12N_YY 0 IO_L12P_YY 0 IO_VREF_L13N_YY 0 IO_L13P_YY 0 IO_L14N_Y 0 IO_L14P_Y 0 IO_VREF_L15N_Y 0 IO_L15P_Y 0 IO_LVDS_DLL_L16N 1 GCK2 ...

Page 112

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 2 IO_L41N_Y 2 IO_VREF_L42P_Y 2 IO_L42N_Y 2 IO_VREF_L43P_YY 2 IO_D1_L43N_YY 2 IO_D2_L44P_YY 2 IO_L44N_YY 2 IO_L45P_Y 2 IO_L45N_Y 2 IO_L46P_Y 2 IO_L46N_Y 2 ...

Page 113

R Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 4 IO_L70N_Y 4 IO_L71P_YY 4 IO_L71N_YY 4 IO_VREF_L72P_YY 4 IO_L72N_YY 4 IO_L73P_Y 4 IO_L73N_Y 4 IO_L74P_YY 4 IO_L74N_YY 4 IO_VREF_L75P_YY 4 IO_L75N_YY 4 IO_L76P_Y 4 IO_L76N_Y 4 IO_VREF_L77P_Y 4 ...

Page 114

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description IO_L103N_YY 6 IO_L103P_YY 6 IO_L104N 6 IO_L104P 6 IO_L105N_Y 6 IO_L105P_Y 6 ...

Page 115

R Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 7 IO_L132P_Y 7 IO_L133N 7 IO_L133P 7 IO_L134N_Y 7 IO_VREF_L134P_Y 7 IO_L135N_Y 7 IO_L135P_Y 7 IO_L136N 7 IO_L136P 2 CCLK 3 DONE NA DXN NA DXP ...

Page 116

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 6 VCCO 7 VCCO 7 VCCO 7 VCCO NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...

Page 117

R BG432 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also Vir- tex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO ...

Page 118

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 13: BG432 Differential Pin Pair Summary XCV300E, XCV400E, XC600E Pair Bank P N Pin Pin ...

Page 119

... DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays BG560 Ball Grid Array Packages XCV1000E, XCV1600E, and XCV2000E devices in BG560 AO Other Ball Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless Functions device-dependent as indicated in the footnotes ...

Page 120

... IO_L20P_Y 0 IO_LVDS_DLL_L21N 0 IO_VREF 1 GCK2 IO_LVDS_DLL_L21P 1 IO_VREF_L22N_Y 1 IO_L22P_Y 1 IO_L23N_Y 1 IO_VREF_L23P_Y 1 IO_L24N_Y 1 IO_L24P_Y 1 IO_L25N_Y Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank B24 1 E22 1 C23 1 A23 1 D22 1 E21 3 1 B22 1 D21 1 C21 1 B21 1 E20 1 D20 1 C20 1 B20 1 E19 ...

Page 121

... IO_L50N_Y 2 IO_VREF_L51P_YY 2 IO_L51N_YY 2 IO_L52P_Y 2 IO_VREF_L52N_Y 2 IO_L53P_Y 2 IO_L53N_Y 2 IO_VREF_L54P_Y 2 IO_L54N_Y 2 IO_L55P_Y 2 IO_L55N_Y 2 IO_VREF_L56P_YY 2 IO_D1_L56N_YY 2 IO_D2_L57P_YY 2 IO_L57N_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank ...

Page 122

... IO_VREF_L82N_Y 3 IO_L83P_Y 3 IO_L83N_Y 3 IO_L84P_Y 3 IO_VREF_L84N_Y 3 IO_L85P_YY 3 IO_VREF_L85N_YY 3 IO_L86P_Y 3 IO_L86N_Y 3 IO_L87P_Y 3 IO_L87N_Y 3 IO_L88P_Y 3 IO_VREF_L88N_Y 3 IO_L89P_Y 3 IO_L89N_Y 3 IO_L90P_Y Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank AA1 Y5 4 AA3 4 AA4 3 4 AB3 4 AA5 4 AC1 4 AB4 4 AC3 4 AB5 4 AC4 4 ...

Page 123

... IO_LVDS_DLL_L115N 5 IO_VREF 5 IO_L116P_Y 5 IO_VREF_L116N_Y 5 IO_L117P_Y 5 IO_L117N_Y 5 IO_L118P_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank AJ12 5 AN11 5 AK12 5 AL12 5 AM12 5 AK13 3 5 AL13 ...

Page 124

... IO_L144N_Y 6 IO_VREF_L144P_Y 6 IO_L145N_Y 6 IO_L145P_Y 6 IO_VREF_L146N_Y 6 IO_L146P_Y 6 IO_L147N_Y 6 IO_L147P_Y 6 IO_VREF_L148N_YY 6 IO_L148P_YY 6 IO_L149N_YY 6 IO_L149P_YY 6 IO_L150N_Y 6 IO_L150P_Y Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank AM31 6 AK28 AE33 6 AF31 6 AJ32 6 AL33 6 AH29 6 AJ30 6 AK31 6 AH30 3 6 AG29 6 AJ31 6 AK32 ...

Page 125

... IO_L179N_Y 7 IO_L179P_Y 7 IO_L180N_Y 7 IO_VREF_L180P_Y 7 IO_L181N_Y 7 IO_L181P_Y 7 IO_L182N_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank P32 7 P31 P30 2 P29 3 M32 NA N31 NA N30 NA L33 ...

Page 126

... VCCINT NA VCCINT 0 VCCO 0 VCCO 0 VCCO 0 VCCO 0 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 2 VCCO 2 VCCO 2 VCCO Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank N29 2 N33 U30 Y31 3 AB2 3 AB32 4 AD2 4 AD32 4 AG3 4 AG31 4 AJ13 5 AK8 5 AK11 ...

Page 127

... G33 NA J32 M33 Notes I/O option only in the XCV2000E; otherwise, I/O REF P1 option only I/O option only in the XCV1600E & 2000E; P33 REF otherwise, I/O option only. R32 I/O option only in the XCV1000E, 1600E, & 2000E; REF otherwise, I/O option only. ...

Page 128

... A25 E23 11 0 B24 D23 12 0 C23 E22 13 0 D22 A23 14 0 B22 E21 15 0 C21 D21 Module Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pair Other 23 AO Functions IO_DLL_L15P 26 NA IO_DLL_L15N 27 NA IO_DLL_L21P 28 NA IO_DLL_L21N 29 ...

Page 129

... AA1 AA3 AA4 77 3 AB3 AA5 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Other AO Functions Pair VREF √ VREF 82 17 VREF VREF 85 19 ...

Page 130

... AN31 AJ27 136 5 AM31 AK28 137 6 AJ30 AH29 138 6 AH30 AK31 139 6 AJ31 AG29 Module Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Other AO Functions Pair √ - 140 √ VREF 141 1 - 142 7 - 143 7 VREF 144 2 VREF 145 ...

Page 131

... R Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 171 7 J33 M29 172 7 K31 L30 173 7 H33 L29 174 7 H32 J31 175 7 H31 K29 176 7 G32 J30 177 7 G31 J29 178 7 E32 E33 179 ...

Page 132

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description 1 IO_L11N_Y 1 IO_L11P_Y 1 IO_L12N_YY 1 IO_L12P_YY 1 IO_L13N_YY 1 IO_VREF_L13P_YY 1 IO_L14N_Y 1 IO_L14P_Y 1 IO_L15N_YY 1 IO_VREF_L15P_YY 1 ...

Page 133

R Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description 4 IO_L43P_Y 4 IO_VREF_L43N_Y 4 IO_L44P_YY 4 IO_L44N_YY 4 IO_VREF_L45P_YY 4 IO_L45N_YY 4 IO_L46P_Y 4 IO_L46N_Y 4 IO_VREF_L47P_YY 4 IO_L47N_YY 4 IO_L48P_YY 4 IO_L48N_YY 4 IO_L49P_Y 4 ...

Page 134

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description 7 IO_L74N_Y 7 IO_VREF_L74P_Y 7 IO_L75N_YY 7 IO_L75P_YY 7 IO_L76N 7 IO_L76P 7 IO_L77N_YY 7 IO_L77P_YY 7 IO_L78N_Y 7 IO_VREF_L78P_Y 7 ...

Page 135

R Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...

Page 136

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 17: FG256 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E, XCV300E P N Pair Bank Pin Pin 19 2 C15 D14 20 2 B16 E13 21 2 C16 E14 22 2 F13 E15 ...

Page 137

R FG456 Fine-Pitch Ball Grid Array Packages XCV200E and XCV300E devices in FG456 fine-pitch Ball Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in both devices pro- vided in this package. If the pin ...

Page 138

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Bank Pin Description 1 IO_L23P_Y 1 IO_L24N_YY 1 IO_VREF_L24P_YY 1 IO_L25N_YY 1 IO_L25P_YY 1 IO_L26N_YY 1 IO_VREF_L26P_YY 1 IO_L27N_YY 1 IO_L27P_YY 1 IO_WRITE_L28N_YY 1 IO_CS_L28P_YY 2 ...

Page 139

R Table 18: FG456 — XCV200E and XCV300E Bank Pin Description 3 IO_L50N_YY 3 IO_L51P_YY 3 IO_D5_L51N_YY 3 IO_D6_L52P_Y 3 IO_VREF_L52N_Y 3 IO_L53P_Y 3 IO_L53N_Y 3 IO_L54P_YY 3 IO_L54N_YY 3 IO_L55P_YY 3 IO_VREF_L55N_YY 3 IO_L56P_YY 3 IO_L56N_YY 3 IO_L57P_YY 3 ...

Page 140

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Bank Pin Description 5 IO_L76N_Y 5 IO_L77P_YY 5 IO_VREF_L77N_YY 5 IO_L78P_YY 5 IO_L78N_YY 5 IO_L79P_Y 5 IO_L79N_Y 5 IO_L80P_Y 5 IO_L80N_Y 5 IO_L81P_YY 5 IO_L81N_YY 5 ...

Page 141

R Table 18: FG456 — XCV200E and XCV300E Bank Pin Description IO_L104N_YY 7 IO_L104P_YY 7 IO_L105N_YY 7 IO_L105P_YY 7 IO_L106N_Y 7 IO_L106P_Y 7 IO_L107N_Y 7 IO_VREF_L107P_Y 7 IO_L108N_YY 7 IO_L108P_YY 7 IO_L109N_YY 7 ...

Page 142

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCO_7 NA VCCO_7 NA VCCO_7 NA VCCO_7 NA VCCO_7 NA ...

Page 143

R Table 18: FG456 — XCV200E and XCV300E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...

Page 144

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 19: FG456 Differential Pin Pair Summary XCV200E, XCV300E P N Pair Bank Pin Pin 18 1 C14 B14 19 1 A15 F12 20 1 C15 B15 21 1 E14 A16 22 1 ...

Page 145

R Table 19: FG456 Differential Pin Pair Summary XCV200E, XCV300E P N Pair Bank Pin Pin AB3 ...

Page 146

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 0 IO_L9N 0 IO_L9P 0 IO_L10N 0 IO_VREF_L10P 0 IO_L11N_YY 0 IO_L11P_YY 0 IO_L12N_Y 0 IO_L12P_Y 0 IO_L13N_YY 0 IO_L13P_YY 0 IO_L14N_YY 0 IO_L14P_YY ...

Page 147

R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 1 IO_L40P_YY 1 IO_L41N_YY 1 IO_VREF_L41P_YY 1 IO_L42N_YY 1 IO_L42P_YY 1 IO_L43N_Y 1 IO_L43P_Y 1 IO_WRITE_L44N_YY 1 IO_CS_L44P_YY ...

Page 148

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description IO_L69P_YY 3 IO_L69N_YY 3 IO_L70P_Y 3 IO_VREF_L70N_Y 3 IO_L71P_Y 3 IO_L71N_Y 3 IO_L72P_YY 3 IO_L72N_YY ...

Page 149

R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 4 IO_L98N_YY 4 IO_L99P_YY 4 IO_L99N_YY 4 IO_L100P_Y 4 IO_L100N_Y 4 IO_VREF_L101P_Y 4 IO_L101N_Y 4 IO_L102P 4 IO_L102N 4 IO_L103P 4 IO_VREF_L103N 4 IO_L104P_YY 4 IO_L104N_YY 4 IO_L105P_Y 4 IO_L105N_Y ...

Page 150

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 5 IO_L129N_Y 5 IO_L130P_YY 5 IO_L130N_YY 5 IO_L131P_YY 5 IO_VREF_L131N_YY 5 IO_L132P_YY 5 IO_L132N_YY 5 IO_L133P_YY 5 IO_L133N_YY 5 IO_L134P_YY 5 IO_VREF_L134N_YY 5 IO_L135P_YY ...

Page 151

R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description IO_L160N_YY 7 IO_L160P_YY 7 IO_L161N_YY 7 IO_L161P_YY 7 IO_L162N_Y 7 IO_VREF_L162P_Y ...

Page 152

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description ...

Page 153

R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 0 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 3 VCCO 3 VCCO ...

Page 154

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND ...

Page 155

R FG676 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the pin pair can be used as ...

Page 156

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 21: FG676 Differential Pin Pair Summary XCV400E, XCV600E P N Ban Pair k Pin Pin 52 2 G24 H22 53 2 J21 G25 54 2 G26 J22 55 2 H24 J23 56 ...

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R Table 21: FG676 Differential Pin Pair Summary XCV400E, XCV600E P N Ban Pair k Pin Pin 120 5 AD11 Y12 121 5 AB11 AD10 122 5 AC11 AE10 123 5 AC10 AA11 124 5 Y11 AD9 125 5 AB10 ...

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... Pins labeled I0_VREF can be used as either in all parts unless device-dependent as indi- cated in the footnotes. If the pin is not used used as general I/O. Immediately following Table 23 for Differential Pair information. Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 0 GCK3 0 ...

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... IO_L43N_Y 1 IO_L43P_Y 1 IO_L44N_YY 1 IO_L44P_YY 1 IO_L45N_YY 1 IO_VREF_L45P_YY 1 IO_L46N_Y 1 IO_L46P_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description C5 1 A19 1 C21 1 IO_L48N_YY 2 B19 1 IO_VREF_L48P_YY C19 1 IO_L49N_YY A18 ...

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... IO_L71N 2 IO_L72P 2 IO_L72N 2 IO_VREF_L73P_YY 2 IO_L73N_YY 2 IO_L74P_YY 2 IO_L74N_YY 2 IO_L75P 2 IO_L75N 2 IO_VREF_L76P_YY 2 IO_D1_L76N_YY 2 IO_D2_L77P_YY 2 IO_L77N_YY 2 IO_L78P_Y 2 IO_L78N_Y 2 IO_L79P 2 IO_L79N 2 IO_L80P 2 IO_L80N 2 IO_VREF_L81P_Y Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description IO_L82P_YY E2 2 IO_L82N_YY IO_VREF_L85P_YY F1 2 IO_D3_L85N_YY J3 2 IO_L86P_YY G2 2 IO_L86N_YY ...

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... IO_VREF_L111N_YY 3 IO_L112P 3 IO_L112N 3 IO_L113P 3 IO_VREF_L113N 3 IO_L114P_YY 3 IO_L114N_YY 3 IO_L115P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AA2 3 IO_VREF_L115N_YY AC5 3 IO_L116P_Y AB1 3 IO_L116N_Y AD3 3 AC1 3 AD1 ...

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... IO_L143P_YY 4 IO_L143N_YY 4 IO_VREF_L144P_YY 4 IO_L144N_YY 4 IO_L145P_Y 4 IO_L145N_Y 4 IO_L146P_Y 4 IO_L146N_Y 4 IO_L147P_YY 4 IO_L147N_YY 4 IO_VREF_L148P_YY 4 IO_L148N_YY 4 IO_L149P_Y 4 IO_L149N_Y Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AV8 4 AU9 4 AW8 4 IO_L151P_YY AT10 4 IO_L151N_YY 3 AV9 4 IO_VREF_L152P_YY AU10 4 IO_L152N_YY AW9 4 AT11 4 AV10 4 IO_VREF_L154P AU11 4 AW10 ...

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... IO_L180P_Y 5 IO_L180N_Y 5 IO_L181P_YY 5 IO_VREF_L181N_YY 5 IO_L182P_YY 5 IO_L182N_YY 5 IO_L183P_Y 5 IO_VREF_L183N_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AV26 5 AW27 5 AU26 AV27 6 AT26 6 AW28 6 AU27 6 IO_L185N_YY AV28 ...

Page 164

... IO_L210N_YY 6 IO_L210P_YY 6 IO_L211N 6 IO_L211P 6 IO_L212N 6 IO_L212P 6 IO_VREF_L213N_YY 6 IO_L213P_YY 6 IO_L214N_YY 6 IO_L214P_YY 6 IO_VREF_L215N 6 IO_L215P Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AH39 7 IO_L216N_YY AG38 7 IO_L216P_YY AG36 7 AG39 7 IO_VREF_L217P AG37 7 IO_L218N_YY AF39 7 IO_L218P_YY AF36 7 IO_L219N_YY AE38 7 IO_VREF_L219P_YY AF37 7 AF38 7 1 AE39 ...

Page 165

... IO_L246P_Y 2 CCLK 3 DONE NA DXN NA DXP PROGRAM NA TCK DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description K38 NA L37 2 J39 NA L36 J38 NA K37 NA H39 NA 3 K36 NA H38 NA ...

Page 166

... VCCO 2 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 4 VCCO 4 VCCO 4 VCCO 4 VCCO 4 VCCO 4 VCCO 5 VCCO 5 VCCO 5 VCCO 5 VCCO 5 VCCO Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description 5 E34 6 E33 6 E30 6 E29 6 E27 6 E26 6 E10 7 E11 7 E13 7 E14 AP5 ...

Page 167

... I/O option only in the XCV1000E, 1600E, 2000E; REF AW2 otherwise, I/O option only I/O option only in the XCV1600E, 2000E; otherwise, REF AW1 I/O option only. AV39 I/O option only in the XCV2000E; otherwise, I/O REF option only. AV38 AV2 AV1 AU39 AU37 AU3 AU20 AU1 AT4 AT36 ...

Page 168

... D29 B30 12 0 C29 A30 13 0 B29 A29 14 0 A28 B28 15 0 B27 C28 16 0 A27 D27 17 0 B26 C27 Module Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E Pair Other 26 Functions 27 28 IO_DLL_L29N 29 IO_DLL_L29P 30 IO_DLL_L155N 31 IO_DLL_L155P VREF 36 √ ...

Page 169

... DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E Other Functions Pair √ VREF 86 √ √ VREF 90 √ VREF √ √ DIN VREF VREF 99 √ - 100 ...

Page 170

... AV16 149 4 AR18 AW16 150 4 AT18 AV17 151 4 AU18 AW17 152 4 AT19 AV18 153 4 AU19 AW18 Module Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E Other Functions Pair 4 - 154 4 VREF 155 6 - 156 √ INIT 157 √ - 158 5 - 159 5 VREF 160 √ ...

Page 171

... AO in the XCV1000E, 1600E, 2000E. √ the XCV600E, 1000E, 1600E the XCV600E, 1000E. 4 VREF the XCV1000E, 1600E. √ the XCV1000E, 2000E the XCV600E, 1000E, 2000E. 4 VREF the XCV1000E. √ the XCV2000E. - √ VREF www.xilinx.com 1-800-255-7778 P N Bank Pin Pin AO √ 7 R39 V35 √ 7 U36 ...

Page 172

... IO_L1N_Y 0 IO_L1P_Y 0 IO_VREF_L2N_Y 0 IO_L2P_Y 0 IO_L3N_Y 0 IO_L3P_Y 0 IO_L4N_YY 0 IO_L4P_YY 0 IO_VREF_L5N_YY 0 IO_L5P_YY 0 IO_L6N_Y 0 IO_L6P_Y 0 IO_L7N_Y 0 IO_L7P_Y 0 IO_L8N_YY Module Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank can be used as gen- 0 24, see Table 25 for Pin # 0 C22 0 A26 0 B31 0 B34 0 C24 0 C29 0 C34 0 D24 0 D36 0 D40 ...

Page 173

... IO_LVDS_DLL_L34P 1 IO_L35N_Y 1 IO_VREF_L35P_Y 1 IO_L36N_Y 1 IO_L36P_Y 1 IO_L37N_YY 1 IO_VREF_L37P_YY 1 IO_L38N_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description D27 1 B25 1 A25 1 D26 1 A24 1 E25 1 D25 1 IO_VREF_L41P_YY B24 ...

Page 174

... IO_L60P_YY 1 IO_L61N_Y 1 IO_L61P_Y 1 IO_L62N_Y 1 IO_L62P_Y 1 IO_L63N_YY 1 IO_VREF_L63P_YY 1 IO_L64N_YY 1 IO_L64P_YY 1 IO_L65N_Y 1 IO_L65P_Y 1 IO_L66N_Y 1 IO_VREF_L66P_Y 1 IO_L67N_Y 1 IO_L67P_Y 1 IO_L68N_Y 1 IO_L68P_Y 1 IO_WRITE_L69N_YY 1 IO_CS_L69P_YY Module Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description A12 IO_DOUT_BUSY_L70P_YY C12 2 IO_DIN_D0_L70N_YY B12 A11 IO_VREF_L73P_Y A10 B10 IO_VREF_L76P_Y IO_VREF_L80P_YY ...

Page 175

... IO_VREF_L98P_YY 2 IO_D3_L98N_YY 2 IO_L99P_YY 2 IO_L99N_YY 2 IO_L100P_Y 2 IO_L100N_Y 2 IO_L101P_Y 2 IO_L101N_Y 2 IO_VREF_L102P_YY 2 IO_L102N_YY 2 IO_L103P_YY 2 IO_L103N_YY 2 IO_VREF_L104P_Y 2 IO_L104N_Y 2 IO_L105P_YY 2 IO_L105N_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description IO_VREF_L106N_Y ...

Page 176

... IO_L129P_YY 3 IO_L129N_YY 3 IO_L130P_YY 3 IO_VREF_L130N_YY 3 IO_L131P_Y 3 IO_L131N_Y 3 IO_L132P_Y 3 IO_L132N_Y 3 IO_L133P_YY 3 IO_L133N_YY 3 IO_L134P_Y 3 IO_VREF_L134N_Y 3 IO_L135P_Y 3 IO_L135N_Y Module Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AJ5 3 AG2 3 AK4 3 AG3 3 IO_VREF_L137N_Y AL4 3 AH1 3 AL5 3 AH2 3 AM4 3 IO_D7_L140P_YY AH3 3 IO_INIT_L140N_YY AM5 AJ1 4 AN3 ...

Page 177

... IO_L162P_Y 4 IO_L162N_Y 4 IO_L163P_Y 4 IO_L163N_Y 4 IO_L164P_YY 4 IO_L164N_YY 4 IO_VREF_L165P_YY 4 IO_L165N_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AW7 4 AY7 4 BB8 4 BA9 4 AV8 4 AW8 4 BA10 4 IO_VREF_L169P_YY BB10 ...

Page 178

... IO_L189P_Y 5 IO_L189N_Y 5 IO_L190P_Y 5 IO_L190N_Y 5 IO_L191P_Y 5 IO_L191N_Y 5 IO_L192P_Y 5 IO_L192N_Y 5 IO_L193P_YY 5 IO_L193N_YY 5 IO_L194P_YY 5 IO_VREF_L194N_YY 5 IO_L195P_Y 5 IO_L195N_Y 5 IO_L196P_Y Module Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description BB23 5 AW23 5 AV23 5 IO_VREF_L197N_YY BA23 5 AW24 5 BB24 5 AY24 5 IO_VREF_L199N_Y AW25 5 BA24 5 AV25 5 AW26 5 IO_VREF_L201N_YY AY25 5 ...

Page 179

... IO_L222P_YY 6 IO_VREF_L223N_Y 6 IO_L223P_Y 6 IO_L224N_Y 6 IO_L224P_Y 6 IO_VREF_L225N_YY 6 IO_L225P_YY 6 IO_L226N_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AJ40 6 AL41 6 AN38 6 AN42 6 IO_VREF_L228N_YY AP41 6 AR39 6 AV41 6 AV42 ...

Page 180

... IO_L249N_YY 7 IO_VREF_L249P_YY 7 IO_L250N_Y 7 IO_L250P_Y 7 IO_L251N_Y 7 IO_L251P_Y 7 IO_L252N_YY 7 IO_L252P_YY 7 IO_L253N_YY 7 IO_VREF_L253P_YY 7 IO_L254N_Y 7 IO_L254P_Y 7 IO_L255N_Y 7 IO_L255P_Y 7 IO_L256N_YY Module Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description 1 AB40 7 AC39 7 7 IO_VREF_L257P_Y F38 7 H40 7 H41 7 J42 7 K39 7 L42 7 N40 7 T40 7 U40 7 V38 7 W42 ...

Page 181

... VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description G38 NA G42 NA G41 NA F40 NA F42 NA F41 NA F39 NA E42 NA ...

Page 182

... VCCO_3 NA VCCO_3 NA VCCO_3 NA VCCO_3 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 Module Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description F15 NA F19 NA F20 AC6 NA AD6 NA AH6 NA AJ6 AL6 NA AM6 NA AR6 ...

Page 183

... AY42 NA AY41 NA AY40 NA AY3 Notes I/O option only in the XCV1600E, 2000E; otherwise, REF AY2 I/O option only I/O option only in the XCV2000E; otherwise, I/O AY1 REF option only. AW42 AW4 AW39 AW1 AV5 AV38 AV30 www.xilinx.com 1-800-255-7778 Pin # GND AV22 GND ...

Page 184

... C31 12 0 A31 E34 13 0 C30 D34 14 0 E33 B30 15 0 D33 A30 16 0 B29 C33 17 0 A29 E32 Module Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E Pair Other 26 AO Functions IO_DLL_L34N 29 NA IO_DLL_L34P 30 NA IO_DLL_L176N 31 NA IO_DLL_L176P 32 33 ...

Page 185

... DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E Other AO Functions Pair √ VREF √ VREF 89 √ VREF √ VREF 93 √ √ VREF 97 √ VREF 100 1 - 101 ...

Page 186

... BB8 149 4 BA9 AV8 150 4 AW8 BA10 151 4 BB10 AY8 152 4 AV9 BA11 153 4 BB11 AW9 Module 100 Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E Other AO Functions Pair 1 - 154 3 - 155 √ D5 156 √ VREF 157 2 - 158 √ - 159 √ ...

Page 187

... AT38 219 6 AT39 AN41 220 6 AM40 AT40 221 6 AM41 AR38 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E Other AO Functions Pair √ - 222 5 - 223 1 - 224 1 - 225 ...

Page 188

... E40 280 7 D41 E39 Notes the XCV1000E, 2000E the XCV1000E, 1600E the XCV2000E the XCV1600E the XCV1000E. Module 102 FG900 Fine-Pitch Ball Grid Array Package XCV600E, XCV1000E, and XCV1600E devices in the Other FG900 fine-pitch Ball Grid Array package have footprint compatibility. Pins labeled I0_VREF can be used as either ...

Page 189

R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 0 IO_L6N_Y 0 IO_L6P_Y 0 IO_L7N_Y 0 IO_L7P_Y 0 IO_L8N_YY 0 IO_L8P_YY 0 IO_VREF_L9N_YY 0 IO_L9P_YY 0 IO_L10N_Y 0 IO_L10P_Y 0 IO_L11N_Y 0 IO_L11P_Y 0 IO_L12N_YY 0 IO_L12P_YY 0 ...

Page 190

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description IO_LVDS_DLL_L34P 1 IO_L35N_YY 1 IO_VREF_L35P_YY 1 IO_L36N_YY 1 IO_L36P_YY 1 IO_L37N_YY 1 IO_VREF_L37P_YY 1 IO_L38N_YY 1 IO_L38P_YY 1 ...

Page 191

R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description ...

Page 192

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 2 IO_L99P_YY 2 IO_L99N_YY 2 IO_L100P 2 IO_L100N 2 IO_L101P_YY 2 IO_L101N_YY 2 IO_VREF_L102P_YY 2 IO_L102N_YY 2 IO_L103P_YY 2 IO_L103N_YY 2 IO_VREF_L104P_YY 2 ...

Page 193

R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 3 IO_L127P_YY 3 IO_VREF_L127N_YY 3 IO_L128P_YY 3 IO_L128N_YY 3 IO_L129P 3 IO_L129N 3 IO_L130P_YY 3 IO_L130N_YY 3 IO_L131P_YY 3 IO_VREF_L131N_YY 3 IO_L132P 3 IO_L132N 3 IO_L133P_YY 3 IO_L133N_YY 3 ...

Page 194

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 4 IO_L154N 4 IO_L155P_YY 4 IO_L155N_YY 4 IO_VREF_L156P_YY 4 IO_L156N_YY 4 IO_L157P 4 IO_L157N 4 IO_L158P_YY 4 IO_L158N_YY 4 IO_L159P 4 IO_VREF_L159N 4 ...

Page 195

R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 5 IO_L182N 5 IO_L183P 5 IO_L183N 5 IO_L184P_YY 5 IO_VREF_L184N_YY 5 IO_L185P_YY 5 IO_L185N_YY 5 IO_L186P 5 IO_L186N 5 IO_L187P 5 IO_L187N 5 IO_L188P_YY 5 IO_VREF_L188N_YY 5 IO_L189P_YY 5 ...

Page 196

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description IO_L212N_YY 6 IO_L212P_YY 6 IO_L213N 6 IO_L213P 6 IO_L214N 6 IO_L214P 6 IO_VREF_L215N_YY 6 IO_L215P_YY 6 ...

Page 197

R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description ...

Page 198

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 7 IO_L275N_YY 7 IO_L275P_YY 7 IO_L276N_YY 7 IO_L276P_YY 7 IO_L277N 7 IO_VREF_L277P 7 IO_L278N_YY 7 IO_L278P_YY 7 IO_L279N_Y 7 IO_L279P_Y 7 IO_L280N_YY 7 ...

Page 199

R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description NA VCCO_0 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA ...

Page 200

Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...

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