XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 11

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals can be configured to oper-
ate asynchronously. All of the control signals are indepen-
dently invertible, and are shared by the two flip-flops within
the slice.
Additional Logic
The F5 multiplexer in each slice combines the function gen-
erator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Each CLB has four direct feedthrough paths, two per slice.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Virtex-E CLB
supports two separate carry chains, one per Slice. The
height of the carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation. The dedicated carry path can also be used
to cascade function generators for implementing wide logic
functions.
BUFTs
Each Virtex-E CLB contains two 3-state drivers (BUFTs)
that can drive on-chip buses. See
Each Virtex-E BUFT has an independent 3-state control pin
and an independent input pin.
Block SelectRAM
Virtex-E FPGAs incorporate large block SelectRAM memo-
ries. These complement the Distributed SelectRAM memo-
ries that provide shallow RAM structures implemented in
CLBs.
Block SelectRAM memory blocks are organized in columns,
starting at the left (column 0) and right outside edges and
inserted every 12 CLB columns (see notes for smaller
devices). Each memory block is four CLBs high, and each
memory column extends the full height of the chip, immedi-
ately adjacent (to the right, except for column 0) of the CLB
column locations indicated in
DS022-2 (v2.8) January 16, 2006
Production Product Specification
R
Table
3.
Dedicated
Routing.
www.xilinx.com
Table 3: CLB/Block RAM Column Locations
Table 4
is available in each Virtex-E device.
Table 4: Virtex-E Block SelectRAM Amounts
As illustrated in
fully synchronous dual-ported (True Dual Port) 4096-bit
RAM with independent control signals for each port. The
data widths of the two ports can be configured indepen-
dently, providing built-in bus-width conversion.
Device
1000E
1600E
2000E
2600E
3200E
Virtex-E Device # of Blocks Block SelectRAM Bits
100E
200E
300E
400E
600E
XCV
/Col.
50E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV50E
Virtex™-E 1.8 V Field Programmable Gate Arrays
shows the amount of block SelectRAM memory that
0 12 24 36 48 60 72 84 96 108
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Figure
√
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Columns 0, 12, 18, & 30
Columns 0, 12, 30, & 42
Columns 0, 6, 18, & 24
√
√
√
6, each block SelectRAM cell is a
144
160
184
208
16
20
28
32
40
72
96
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√
√
√
√
√
√
√
√
√
√
√
√
√
√
114,688
131,072
163,840
294,912
393,216
589,824
655,360
753,664
851,968
65,536
81,920
120
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√
Module 2 of 4
138
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√
156
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5