XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 16

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Data Registers
The primary data register is the Boundary Scan register.
For each IOB pin in the FPGA, bonded or not, it includes
three bits for In, Out, and 3-State Control. Non-IOB pins
have appropriate partial bit population if input-only or out-
put-only. Each EXTEST CAPTURED-OR state captures all
In, Out, and 3-state pins.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream Boundary Scan
device.
The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respec-
tively. For these instructions, two corresponding pins (T
DO1 and TDO2) allow user scan data to be shifted out of
TDO.
Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).
Bit Sequence
The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the Boundary
Scan I/O data register, while the output-only pins contrib-
utes all three bits.
From a cavity-up view of the chip (as shown in EPIC), start-
ing in the upper right chip corner, the Boundary Scan
data-register bits are ordered as shown in
Module 2 of 4
10
Figure 12: Boundary Scan Bit Sequence
Bit 0 ( TDO end)
Bit 1
Bit 2
(TDI end)
Right half of top-edge IOBs (Right to Left)
GCLK2
GCLK3
Left half of top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
M1
M0
M2
Left half of bottom-edge IOBs (Left to Right)
GCLK1
GCLK0
Right half of bottom-edge IOBs (Left to Right)
DONE
PROG
Right-edge IOBs (Bottom to Top)
CCLK
990602001
Figure
12.
www.xilinx.com
BSDL (Boundary Scan Description Language) files for Vir-
tex-E Series devices are available on the Xilinx web site in
the File Download area.
Identification Registers
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
where
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code (see
stream generation and is valid only after configuration.
Table 7: IDCODEs Assigned to Virtex-E FPGAs
Note:
Including Boundary Scan in a Design
Since the Boundary Scan pins are dedicated, no special
element needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
If an internal data register is used, insert the Boundary Scan
symbol and connect the necessary pins as appropriate.
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
v = the die version number
f = the family code (05 for Virtex-E family)
a = the number of CLB rows (ranges from 16 for
XCV50E to 104 for XCV3200E)
c = the company code (49h for Xilinx)
Attempting to load an incorrect bitstream causes
configuration to fail and can damage the device.
Table
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV50E
FPGA
7) is embedded in the bitstream during bit-
Production Product Specification
DS022-2 (v2.8) January 16, 2006
v0A5C093h
v0A1C093h
v0A10093h
v0A14093h
v0A20093h
v0A28093h
v0A30093h
v0A40093h
v0A48093h
v0A50093h
v0A68093h
IDCODE
R