XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 26

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL applica-
tion as shown in
This symbol does not provide access to the advanced clock
domain controls or to the clock multiplication or clock divi-
sion features of the DLL. This symbol also does not provide
access to the RST, or LOCKED pins of the DLL. For access
to these features, a designer must use the library DLL prim-
itives described in the following sections.
Source Clock Input — I
The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the BUF-
GDLL macro the source clock frequency must fall in the low
frequency range as specified in the data sheet. The BUF-
Module 2 of 4
20
Figure 23: High Frequency DLL Symbol CLKDLLHF
Figure 22: Standard DLL Symbol CLKDLL
I
IBUFG
Figure 24: BUFGDLL Schematic
O
Figure
CLKIN
CLKFB
RST
CLKIN
CLKFB
RST
CLKIN
CLKFB
RST
24.
CLKDLLHF
CLKDLL
CLKDLL
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLK0
CLK180
CLKDV
LOCKED
ds022_027_121099
ds022_26_121099
I
BUFG
ds022_28_121099
O
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GDLL requires an external signal source clock. Therefore,
only an external input port can source the signal that drives
the BUFGDLL I pin.
Clock Output — O
The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced by
a global clock buffer BUFG symbol, takes advantage of the
dedicated global clock routing resources of the device.
The output clock has a 50-50 duty cycle unless you deacti-
vate the duty cycle correction property.
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the com-
plete set of DLL features needed when implementing more
complex applications with the DLL.
Source Clock Input — CLKIN
The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL,
one of the global clock input buffers (IBUFG), or an
IO_LVDS_DLL pin on the same edge of the device (top or
bottom) must source this clock signal. There are four
IO_LVDS_DLL input pins that can be used as inputs to the
DLLs. This makes a total of eight usable input pins for DLLs
in the Virtex-E family.
Feedback Clock Input — CLKFB
The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. The feed-
back clock input can also be provided through one of the fol-
lowing pins.
If an IBUFG sources the CLKFB pin, the following special
rules apply.
1. An external input port must source the signal that drives
2. The CLK2X output must feedback to the device if both
3. That signal must directly drive only OBUFs and nothing
These rules enable the software determine which DLL clock
output sources the CLKFB pin.
Reset Input — RST
When the reset pin RST activates the LOCKED signal deac-
tivates within four source clock cycles. The RST pin, active
High, must either connect to a dynamic signal or tied to
IBUFG - Global Clock Input Pad
IO_LVDS_DLL - the pin adjacent to IBUFG
the IBUFG I pin.
the CLK0 and CLK2X outputs are driving off chip
devices.
else.
Production Product Specification
DS022-2 (v2.8) January 16, 2006
R