XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 28

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
DLL Properties
Properties provide access to some of the Virtex-E series
DLL features, (for example, clock division and duty cycle
correction).
Duty Cycle Correction Property
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, exhibiting a 50/50 duty
cycle. The DUTY_CYCLE_CORRECTION property (by
default TRUE) controls this feature. To deactivate the DLL
duty-cycle correction for the 1x clock outputs, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol.
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
Startup Delay Property
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the device con-
figuration DONE signal waits until the DLL locks before
going to High.
Virtex-E DLL Location Constraints
As shown in
Virtex-E devices, for a total of eight per Virtex-E device.
These DLLs are located in silicon, at the top and bottom of
the two innermost block SelectRAM columns. The location
constraint LOC, attached to the DLL symbol with the identi-
fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,
or DLL3P, controls the DLL location.
The LOC property uses the following form:
LOC = DLL0P
Design Factors
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Module 2 of 4
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DLL-3S
DLL-1S
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Figure
Figure 26: Virtex Series DLLs
DLL-3P
DLL-1P
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26, there are four additional DLLs in the
DLL-2P
DLL-0P
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DLL-2S
DLL-0S
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Bottom Right
Half Edge
x132_14_100799
www.xilinx.com
Input Clock
The output clock signal of a DLL, essentially a delayed ver-
sion of the input clock signal, reflects any instability on the
input clock in the output waveform. For this reason the qual-
ity of the DLL input clock relates directly to the quality of the
output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the data sheet.
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially available
quartz crystal oscillator. For example, most crystal oscilla-
tors produce an output waveform with a frequency tolerance
of 100 PPM, meaning 0.01 percent change in the clock
period. The DLL operates reliably on an input waveform with
a frequency drift of up to 1 ns — orders of magnitude in
excess of that needed to support any crystal oscillator in the
industry. However, the cycle-to-cycle jitter must be kept to
less than 300 ps in the low frequencies and 150 ps for the
high frequencies.
Input Clock Changes
Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL produces an unreliable lock signal and out-
put clock.
It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100 μs to keep device cooling to a minimum. The clock
should be stopped during a Low phase, and when restored
the full High period should be seen. During this time,
LOCKED stays High and remains High when the clock is
restored.
When the clock is stopped, one to four more clocks are still
observed as the delay line is flushed. When the clock is
restarted, the output clocks are not observed for one to four
clocks as the delay line is filled. The most common case is
two or three clocks.
In a similar manner, a phase shift of the input clock is also
possible. The phase shift propagates to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control.
Output Clocks
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or they can route directly to destination
clock pins. The only BUFGs that the DLL clock outputs can
drive are the two on the same edge of the device (top or bot-
tom). In addition, the CLK2X output of the secondary DLL
can connect directly to the CLKIN of the primary DLL in the
same quadrant.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
Production Product Specification
DS022-2 (v2.8) January 16, 2006
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