XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 29

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Useful Application Examples
The Virtex-E DLL can be used in a variety of creative and
useful applications. The following examples show some of
the more common applications. The Verilog and VHDL
example files are available at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Standard Usage
The circuit shown in
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
Board Level Deskew of Multiple Non-Virtex-E
Devices
The circuit shown in
system clock between a Virtex-E chip and other non-Vir-
tex-E chips on the same board. This application is com-
monly used when the Virtex-E device is used in conjunction
with other standard products such as SRAM or DRAM
devices. While designing the board level route, ensure that
the return net delay to the source equals the delay to the
other chips involved.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Figure 27: Standard DLL Implementation
R
IBUFG
IBUF
CLKIN
CLKFB
RST
Figure 28
Figure 27
CLKDLL
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
can be used to deskew a
resembles the BUFGDLL
BUFG
OBUF
ds022_028_121099
www.xilinx.com
Board-level deskew is not required for low-fanout clock net-
works. It is recommended for systems that have fanout lim-
itations on the clock network, or if the clock distribution chip
cannot handle the load.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
The dll_mirror_1 files in the
VHDL and Verilog implementation of this circuit.
Deskew of Clock and Its 2x Multiple
The circuit shown in
plier and also uses the CLK0 clock output with a zero ns
skew between registers on the same chip. Alternatively, a
clock divider circuit can be implemented using similar con-
nections.
Figure 29: DLL Deskew of Clock and 2x Multiple
Figure 28: DLL Deskew of Board Level Clock
Virtex™-E 1.8 V Field Programmable Gate Arrays
Other Non_Virtex-E Chips
Virtex-E Device
IBUFG
IBUF
IBUFG
IBUFG
Non-Virtex-E Chip
Non-Virtex-E Chip
Figure 29
CLKIN
CLKFB
RST
CLKIN
CLKFB
RST
CLKIN
CLKFB
RST
CLKDLL
CLKDLL
CLKDLL
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
implements a 2x clock multi-
xapp132.zip
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
ds022_029_121099
BUFG
OBUF
BUFG
OBUF
BUFG
ds022_030_121099
file show the
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