XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 30

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Because any single DLL can access only two BUFGs at
most, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
The dll_2x files in the
Verilog implementation of this circuit.
Virtex-E 4x Clock
Two DLLs located in the same half-edge (top-left, top-right,
bottom-right, bottom-left) can be connected together, with-
out using a BUFG between the CLKDLLs, to generate a 4x
clock as shown in
devices, have four clock networks that are available for inter-
nal deskewing of the clock. Each of the eight DLLs have
access to two of the four clock networks. Although all the
DLLs can be used for internal deskewing, the presence of
two GCLKBUFs on the top and two on the bottom indicate
that only two of the four DLLs on the top (and two of the four
DLLs on the bottom) can be used for this purpose.
The dll_4xe files in the xapp132.zip file show the DLL imple-
mentation in Verilog for Virtex-E devices. These files can be
found at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Using Block SelectRAM+ Features
The Virtex FPGA Series provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block SelectRAM+
memory can be independently configured as a read/write
port, a read port, a write port, and can be configured to a
specific data width. The block SelectRAM+ memory offers
Module 2 of 4
24
Figure 30: DLL Generation of 4x Clock in Virtex-E
IBUFG
Figure
RST
RST
xapp132.zip
CLKIN
CLKFB
CLKIN
CLKFB
CLKDLL-S
CLKDLL-P
30. Virtex-E devices, like the Virtex
Devices
LOCKED
LOCKED
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
file show the VHDL and
BUFG
OBUF
ds022_031_041901
INV
www.xilinx.com
new capabilities allowing the FPGA designer to simplify
designs.
Operating Modes
VIrtex-E block SelectRAM+ memory supports two operating
modes:
•
•
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on whether a faster clock-to-out versus
set-up time is desired. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the
read pulse clock.
Write Back (one clock edge)
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
Block SelectRAM+ Characteristics
•
•
•
•
•
•
The output ports are latched with a self timed circuit to guar-
antee a glitch free read. The state of the output port does
not change until the port executes another read or write
operation.
Library Primitives
Figure 31
SelectRAM+ primitives.
able primitives for synthesis and simulation.
Read Through
Write Back
All inputs are registered with the port clock and have a
set-up to clock timing specification.
All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
The block SelectRAMs are true SRAM memories and
do not have a combinatorial path from the address to
the output. The LUT SelectRAM+ cells in the CLBs are
still available with this function.
The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
A write operation requires only one clock edge.
A read operation requires only one clock edge.
and
Figure 32
Table 14
show the two generic library block
Production Product Specification
DS022-2 (v2.8) January 16, 2006
describes all of the avail-
R