XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 31

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 14: Available Library Primitives
DS022-2 (v2.8) January 16, 2006
Production Product Specification
RAMB4_S1
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
RAMB4_S2
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
RAMB4_S4
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
RAMB4_S16
RAMB4_S16_S16
Figure 32: Single-Port Block SelectRAM+ Memory
Figure 31: Dual-Port Block SelectRAM+ Memory
Primitive
R
WEA
ENA
RSTA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
ADDRB[#:0]
DIB[#:0]
CLKA
CLKB
WE
EN
RST
ADDR[#:0]
DI[#:0]
CLK
RAMB4_S#_S#
RAMB4_S#
Port A Width
16
1
2
4
8
ds022_033_121399
DO[#:0]
DOA[#:0]
DOB[#:0]
ds022_032_121399
Port B Width
N/A
N/A
N/A
N/A
N/A
16
16
16
16
16
1
2
4
8
2
4
8
4
8
8
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Port Signals
Each block SelectRAM+ port operates independently of the
others while accessing the same set of 4096 memory cells.
Table 15
block SelectRAM+ memory.
Table 15: Block SelectRAM+ Port Aspect Ratios
Clock—CLK[A|B]
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time refer-
enced to the CLK pin.
Enable—EN[A|B]
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the mem-
ory cells.
Write Enable—WE[A|B]
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the con-
tents of the memory cells referenced by the address bus
reflect on the data out bus.
Reset—RST[A|B]
The reset pin forces the data output bus latches to zero syn-
chronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
Address Bus—ADDR[A|B]<#:0>
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width, as
shown in
Width
16
1
2
4
8
Virtex™-E 1.8 V Field Programmable Gate Arrays
describes the depth and width aspect ratios for the
Table
15.
Depth
4096
2048
1024
Table
512
256
15.
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
ADDR Bus
DATA<15:0>
DATA<1:0>
DATA<3:0>
DATA<7:0>
Data Bus
DATA<0>
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