XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 35

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Initialization in Verilog and Synopsys
The block SelectRAM+ structures can be initialized in Verilog
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a def-
param to pass the initialization. The Synopsys FPGA com-
piler does not presently support defparam. The initialization
values instead attach as attributes to the RAM by a built-in
Synopsys dc_script. The translate_off statement stops syn-
thesis translation of the defparam statements. The following
code illustrates a module that employs these techniques.
Design Examples
Creating a 32-bit Single-Port RAM
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single port, 128 deep by
32-bit wide RAM to be created using a single block
SelectRAM+ cell as shown in
Interleaving the memory space, setting the LSB of the
address bus of Port A to 1 (V
DS022-2 (v2.8) January 16, 2006
Production Product Specification
ADDR[6:0], GND
ADDR[6:0], V
Figure 35: Single Port 128 x 32 RAM
R
DI[31:16]
DI[15:0]
RST
CLK
RST
CLK
WE
WE
EN
EN
CC
WEA
ENA
RSTA
ADDRA[7:0]
DIA[15:0]
WEB
ENB
RSTB
ADDRB[7:0]
DIB[15:0]
CLKA
CLKB
RAMB4_S16_S16
Figure
CC
DOA[15:0]
DOB[15:0]
), and the LSB of the
35.
ds022_036_121399
DO[31:16]
DO[15:0]
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address bus of Port B to 0 (GND), allows a 32-bit wide sin-
gle port RAM to be created.
Creating Two Single-Port RAMs
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single RAM to be split into
two single port memories of 2K bits each as shown in
Figure
In this example, a 512K x 4 RAM (Port A) and a 128 x 16
RAM (Port B) are created out of a single block SelectRAM+.
The address space for the RAM is split by fixing the MSB of
Port A to 1 (V
B to 0 (GND) for the lower 2K bits.
Block Memory Generation
The CoreGen program generates memory structures using
the block SelectRAM+ features. This program outputs
VHDL or Verilog simulation code templates and an EDIF file
for inclusion in a design.
Virtex™-E 1.8 V Field Programmable Gate Arrays
Figure 36: 512 x 4 RAM and 128 x 16 RAM
36.
GND, ADDR2[6:0]
V
CC
, ADDR1[8:0]
CC
DI2[15:0]
DI1[3:0]
RST2
CLK2
RST1
CLK1
WE2
WE1
EN2
EN1
) for the upper 2K bits and the MSB of Port
WEA
ENA
RSTA
ADDRA[9:0]
DIA[3:0]
WEB
ENB
RSTB
ADDRB[7:0]
DIB[15:0]
CLKA
CLKB
RAMB4_S4_S16
DOA[3:0]
DOB[15:0]
ds022_037_121399
DO1[3:0]
DO2[15:0]
Module 2 of 4
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