XCV2000E-8FG1156C Xilinx Inc, XCV2000E-8FG1156C Datasheet - Page 92

• Manufacturer Part Number: XCV2000E-8FG1156C
• Description: IC FPGA 1.8V C-TEMP 1156-BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-8FG1156C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 804
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Module 4 of 4
6
Notes:
1.
2.
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
1
1
2
3
3
4
5
5
6
7
7
V
option only.
V
I/O option only.
REF
REF
or I/O option only in the XCV200E; otherwise, I/O
or I/O option only in the XCV100E, 200E; otherwise,
Pin Description
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
G11
M13
G10
A13
B12
N13
B11
E11
N12
J12
M2
D7
N1
N7
G2
A1
B9
C7
D5
E4
B2
F1
L3
L5
L7
L9
J1
www.xilinx.com
1-800-255-7778
CS144 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 5: CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E
Pair
10
11
12
13
14
15
16
17
0
1
2
3
0
1
2
3
4
5
6
7
8
9
Total Pairs: 30, Asynchronous Output Pairs: 18
Bank
4
5
1
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
3
4
4
4
Global Differential Clock
D10
C11
D13
E12
H12
H10
K10
N10
F10
F13
L11
Pin
J11
M7
D8
D9
N9
K7
A7
A6
A4
A5
B7
P
IO LVDS
Production Product Specification
M11
C10
C12
G13
H11
E10
E13
F11
Pin
J13
J10
L13
M6
N8
B7
C6
B4
B5
C6
C8
C9
K9
K8
N
DS022-4 (v2.5) March 14, 2003
AO
NA
NA
NA
NA
NA
NA
√
√
√
√
√
√
1
√
1
1
√
1
√
√
√
√
IO_LVDS_DLL
IO_DLL_L18P
IO_DLL_L18N
IO_DLL_L2N
IO_DLL_L2P
CS, WRITE
Functions
D1, VREF
D3, VREF
D4, VREF
D6, VREF
DIN, D0
Other
VREF
VREF
VREF
INIT
D2
D5
-
-
-
-
-
R