XC3130A-3PC84C Xilinx Inc, XC3130A-3PC84C Datasheet - Page 19

• Manufacturer Part Number: XC3130A-3PC84C
• Description: IC LOGIC CL ARRAY 3000GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3130A-3PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 74
• Number Of Gates: 2000
• Voltage - Supply: 4.25 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1040

a synchronous start-up sequence and become operational.
See
loading configuration data, the user I/O pins are enabled as
configured. As selected, the internal user-logic RESET is
released either one clock cycle before or after the I/O pins
become active. A similar timing selection is programmable
for the DONE/PROG output signal. DONE/PROG may also
be programmed to be an open drain or include a pull-up
resistor to accommodate wired ANDing. The High During
Configuration (HDC) and Low During Configuration (LDC)
are two user I/O pins which are driven active while an
FPGA is in its Initialization, Clear or Configure states. They
and DONE/PROG provide signals for control of external
logic signals such as RESET, bus enable or PROM enable
during configuration. For parallel Master configuration
modes, these signals provide PROM enable control and
allow the data pins to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs have
TTL thresholds and can change to CMOS thresholds at the
completion of configuration if the user has selected CMOS
thresholds. The threshold of PWRDWN and the direct clock
inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
November 9, 1998 (Version 3.1)
Figure 22: Configuration and Start-up of One or More FPGAs.
DIN
Figure
*
The configuration data consists of a composite
40-bit preamble/length count, followed by one or
more concatenated FPGA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.
Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the I/O outputs
become active.
Heavy lines indicate the default condition
Preamble
22. Two CCLK cycles after the completion of
12
R
Product Obsolete or Under Obsolescence
Length Count
24
4
Start
Bit
Data Frame
Data
XC3000 Series Field Programmable Gate Arrays
Configuration Data
Configuration data to define the function and interconnec-
tion within a Field Programmable Gate Array is loaded from
an external storage at power-up and after a re-program sig-
nal. Several methods of automatic and controlled loading of
the required data are available. Logic levels applied to
mode selection pins at the start of configuration time deter-
mine the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configu-
ration mode. The different FPGAs have different sizes and
numbers of data frames. To maintain compatibility between
various device types, the Xilinx product families use com-
patible configuration formats. For the XC3020A, configura-
tion requires 14779 bits for each device, arranged in 197
data frames. An additional 40 bits are used in the header.
See
produced by the development system and one or more of
these files can then be combined and appended to a length
count preamble and be transformed into a PROM format
file by the development system. A compatibility exception
precludes the use of an XC2000-series device as the mas-
ter for XC3000-series devices if their DONE or RESET are
programmed to occur after their outputs become active.
The Tie Option defines output levels of unused blocks of a
design and connects these to unused routing resources.
This prevents indeterminate levels that might produce par-
asitic supply currents. If unused blocks are not sufficient to
complete the tie, the user can indicate nets which must not
Stop
3
Start
Bit
Figure
22. The specific data format for each device is
Last Frame
Length Count*
Internal Reset
Weak Pull-Up
STOP
PROGRAM
3
Postamble
4
I/O Active
DONE
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