XC3130A-3PC84C Xilinx Inc, XC3130A-3PC84C Datasheet - Page 23

• Manufacturer Part Number: XC3130A-3PC84C
• Description: IC LOGIC CL ARRAY 3000GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3130A-3PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 74
• Number Of Gates: 2000
• Voltage - Supply: 4.25 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1040

Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
November 9, 1998 (Version 3.1)
Figure 23: Master Serial Mode Circuit Diagram
RESISTOR OVERCOMES THE
DURING CONFIGURATION
THE 5 k M2 PULL-DOWN
BUT IT ALLOWS M2 TO
INTERNAL PULL-UP,
5-k RESISTOR IS
R
SERIES WITH M1
IF READBACK IS
ACTIVATED, A
REQUIRED IN
BE USER I/O.
*
Product Obsolete or Under Obsolescence
GENERAL-
PURPOSE
USER I/O
PINS
RESET
+5V
•
•
•
•
•
DOUT
M2
HDC
RESET
LDC
INIT
M0
OTHER
I/O PINS
*
M1
DEVICE
XC3000
FPGA
PWRDWN
(LOW RESETS THE XC17xx ADDRESS POINTER)
+5 V
XC3000 Series Field Programmable Gate Arrays
CCLK
DIN
D/P
INIT
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven from either LDC or
CE
OE/RESET
TO DIN OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
DATA
CLK
+5 V
V CC
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
XC17xx
SCP
V PP
CEO
CE
OE/RESET
DATA
CLK
CASCADED
MEMORY
SERIAL
X5989_01
7-25
7