XC3130A-3PC84C Xilinx Inc, XC3130A-3PC84C Datasheet - Page 53

• Manufacturer Part Number: XC3130A-3PC84C
• Description: IC LOGIC CL ARRAY 3000GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3130A-3PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 74
• Number Of Gates: 2000
• Voltage - Supply: 4.25 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1040

XC3100A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
November 9, 1998 (Version 3.1)
Combinatorial Delay
Sequential delay
Set-up time before clock K
Hold Time after clock K
Clock
Reset Direct (RD)
Global Reset (RESET Pad)
Logic Variables
to outputs X or Y
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
Logic Variables
Data In
Enable Clock
Reset Direct inactive RD
Logic Variables
Data In
Enable Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
RD width
delay from RD to outputs X or Y
RESET width (Low)
delay from RESET pad to outputs X or Y
through function generators F or G to drive
X or Y
1. The CLB K to Q output delay (T
2. T
Data In hold time requirement (T
specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and
0.30 ns (-09).
ILO
, T
R
Description
QLO
and T
A, B, C, D, E,
A, B, C, D, E
DI
EC
A, B, C, D, E
DI
EC
(XC3142A)
Product Obsolete or Under Obsolescence
1
ICK
are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
CKO
CKDI
Speed Grade
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
, #5) of any CLB on the same die.
11
12
13
1
8
2
4
6
3
5
7
9
Symbol
T
T
T
T
T
T
T
T
T
F
T
T
T
T
T
ECCK
CKEC
T
DICK
CKDI
MRW
CKO
RPW
MRQ
QLO
CLK
RIO
ILO
ICK
CKI
CH
CL
14.0
Min
227
2.5
1.6
3.2
1.0
1.0
0.8
2.0
2.0
3.2
0
XC3000 Series Field Programmable Gate Arrays
-4
Max
14.0
3.3
2.5
5.2
3.7
12.0
Min
270
2.1
1.4
2.7
1.0
0.9
0.7
1.6
1.6
2.7
0
-3
Max
12.0
2.7
2.1
4.3
3.1
12.0
Min
323
1.8
1.3
2.5
1.0
0.9
0.7
1.3
1.3
2.3
0
-2
Max
12.0
2.2
1.7
3.5
2.7
12.0
Min
323
1.7
1.2
2.3
1.0
0.8
0.6
1.3
1.3
2.3
0
-1
Max
1.75
12.0
1.4
3.1
2.4
2.05
0.55
2.05
12.0
Min
370
1.5
1.0
1.0
0.7
1.3
1.3
0
Prelim
-09
Max
1.25
2.15
12.0
1.5
2.7
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7-55
7