XC4020E-2HQ240C Xilinx Inc, XC4020E-2HQ240C Datasheet - Page 2

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XC4020E-2HQ240C

Manufacturer Part Number
XC4020E-2HQ240C
Description
IC FPGA 784 CLB'S 240-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4020E-2HQ240C

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
193
Number Of Gates
20000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1116

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speeds to 80 MHz.
XC4000E and XC4000X Series
Compared to the XC4000
For readers already familiar with the XC4000 family of Xil-
inx Field Programmable Gate Arrays, the major new fea-
tures in the XC4000 Series devices are listed in this
section. The biggest advantages of XC4000E and
XC4000X devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory.
also offer many new routing features, including special
high-speed clock buffers that can be used to capture input
data with minimal delay.
Any XC4000E device is pinout- and bitstream-compatible
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
XC4000X Series devices are not bitstream-compatible with
equivalent array size devices in the XC4000 or XC4000E
families. However, equivalent array size devices, such as
the XC4025, XC4025E, XC4028EX, and XC4028XL, are
pinout-compatible.
Improvements in XC4000E and XC4000X
Increased System Speed
XC4000E and XC4000X devices can run at synchronous
system clock rates of up to 80 MHz, and internal perfor-
mance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both
device processing and system architecture.
Series devices use a sub-micron multi-layer metal process.
In addition, many architectural improvements have been
made, as described below.
The XC4000XL family is a high performance 3.3V family
based on 0.35 SRAM technology and supports system
PCI Compliance
XC4000 Series -2 and faster speed grades are fully PCI
compliant. XC4000E and XC4000X devices can be used to
implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramati-
cally. Some parameters, such as the delay on the carry
chain through a single CLB (T
May 14, 1999 (Version 1.6)
R
Product Obsolete or Under Obsolescence
BYP
), have improved by as
The XC4000X devices
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000
much as 50% from XC4000 values. See
on page 18
Select-RAM Memory: Edge-Triggered, Synchro-
nous RAM Modes
The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option converts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous Read/Write.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-trig-
gered (synchronous) dual-port RAM, or as combinatorial
logic.
Configurable RAM Content
The RAM content can now be loaded at configuration time,
so that the RAM starts up with user-defined data.
H Function Generator
In current XC4000 Series devices, the H function generator
is more versatile than in the original XC4000. Its inputs can
come not only from the F and G function generators but
also from up to three of the four control input lines. The H
function generator can thus be totally or partially indepen-
dent of the other two function generators, increasing the
maximum capacity of the device.
IOB Clock Enable
The two flip-flops in each IOB have a common clock enable
input, which through configuration can be activated individ-
ually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This new feature makes the IOBs more versatile, and
avoids the need for clock gating.
Output Drivers
The output pull-up structure defaults to a TTL-like
totem-pole. This driver is an n-channel pull-up transistor,
pulling to a voltage one transistor threshold below Vcc, just
like the XC4000 family outputs. Alternatively, XC4000
Series devices can be globally configured with CMOS out-
puts, with p-channel pull-up transistors pulling to Vcc. Also,
the configurable pull-up resistor in the XC4000 Series is a
p-channel transistor that pulls to Vcc, whereas in the origi-
nal XC4000 family it is an n-channel transistor that pulls to
a voltage one transistor threshold below Vcc.
for more information.
“Fast Carry Logic”
6-7
6

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