XC4028EX-3HQ208C Xilinx Inc, XC4028EX-3HQ208C Datasheet - Page 42

• Manufacturer Part Number: XC4028EX-3HQ208C
• Description: IC FPGA 1024 CLB'S 208-HQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4028EX-3HQ208C

• Number Of Logic Elements/cells: 2432
• Number Of Labs/clbs: 1024
• Total Ram Bits: 32768
• Number Of I /o: 160
• Number Of Gates: 28000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1127

XC4000E and XC4000X Series Field Programmable Gate Arrays
Configuration Modes
XC4000E devices have six configuration modes. XC4000X
devices have the same six modes, plus an additional con-
figuration mode. These modes are selected by a 3-bit input
code applied to the M2, M1, and M0 inputs. There are three
self-loading Master modes, two Peripheral modes, and a
Serial
daisy-chained devices. The coding for mode selection is
shown in
Table 18: Configuration Modes
A detailed description of each configuration mode, with tim-
ing information, is included later in this data sheet. During
configuration, some of the I/O pins are used temporarily for
the configuration process. All pins used during configura-
tion are shown in
Master Modes
The three Master modes use an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential slave
devices. They also generate address and timing for exter-
nal PROM(s) containing the configuration data.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte parallel data.
The data is internally serialized into the FPGA data-frame
format. The up and down selection generates starting
addresses at either zero or 3FFFF (3FFFFF when 22
address lines are used), for compatibility with different
microprocessor addressing conventions. The Master Serial
mode generates CCLK and receives the configuration data
in serial form from a Xilinx serial-configuration PROM.
CCLK speed is selectable as either 1 MHz (default) or 8
MHz. Configuration always starts at the default slow fre-
quency, then can switch to the higher frequency during the
first frame. Frequency tolerance is -50% to +25%.
6-46
Master Serial
Slave Serial
Master
Parallel Up
Master
Parallel Down
Peripheral
Synchronous*
Peripheral
Asynchronous
Reserved
Reserved
* Can be considered byte-wide Slave Parallel
Mode
Slave
Table
18.
mode,
M2
Table 22 on page
0
1
1
1
0
1
0
0
M1
0
1
0
1
1
0
1
0
Product Obsolete or Under Obsolescence
which
M0
0
1
0
0
1
1
0
1
is
CCLK
output
output
output
output
input
input
58.
—
—
used
from 3FFFF
primarily
from 00000
Byte-Wide,
Byte-Wide,
decrement
Byte-Wide
Byte-Wide
increment
Bit-Serial
Bit-Serial
Data
—
—
for
Additional Address lines in XC4000 devices
The XC4000X devices have additional address lines
(A18-A21) allowing the additional address space required
to daisy-chain several large devices.
The extra address lines are programmable in XC4000EX
devices. By default these address lines are not activated. In
the default mode, the devices are compatible with existing
XC4000 and XC4000E products. If desired, the extra
address lines can be used by specifying the address lines
option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
via the bitstream, that it should be using all 22 address
lines. Because these pins will initially be pulled high by
internal pull-ups, designers using Master Parallel Up mode
should use external pull down resistors on pins A18-A21. If
Master Parallel Down mode is used external resistors are
not necessary.
All 22 address lines are always active in Master Parallel
modes with XC4000XL devices. The additional address
lines behave identically to the lower order address lines. If
the Address Lines option in bitgen is set to 18, it will be
ignored by the XC4000XL device.
The additional address lines (A18-A21) are not available in
the PC84 package.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake sig-
nal. In Asynchronous Peripheral mode, the internal oscilla-
tor generates a CCLK burst signal that serializes the
byte-wide data. CCLK can also drive slave devices. In the
synchronous mode, an externally supplied clock input to
CCLK serializes the data.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a “daisy chain,” and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in
60. Connect the DOUT of each device to the DIN of the
next. The lead or master FPGA and following slaves each
passes resynchronized configuration data coming from a
single source. The header data, including the length count,
May 14, 1999 (Version 1.6)
Figure 51 on page
R