XC4013E-3PQ240C Xilinx Inc, XC4013E-3PQ240C Datasheet - Page 41
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XC4013E-3PQ240C
Manufacturer Part Number
XC4013E-3PQ240C
Description
IC FPGA C-TEMP 5V 3SPD 240-PQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4013E-3PQ240C
Number Of Logic Elements/cells
1368
Number Of Labs/clbs
576
Total Ram Bits
18432
Number Of I /o
192
Number Of Gates
13000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP
Case
QFP240
Dc
99+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Table 17: Boundary Scan Instructions
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
• TMS: Tie High to put the Test Access Port controller
• TCK: Tie High or Low—don't toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, “ Boundary Scan in
XC4000E Devices .“
May 14, 1999 (Version 1.6)
Figure 42:
Instruction I2
0
0
0
0
1
1
1
1
in a benign RESET state
I1
Bit 0 ( TDO end)
Bit 1
Bit 2
0
0
1
1
0
0
1
1
I0
(TDI end)
0
1
0
1
0
1
0
1
Boundary Scan Bit Sequence
R
CONFIGURE
SAMPLE/PR
READBACK
Reserved
Selected
BYPASS
EXTEST
USER 1
USER 2
ELOAD
Test
Product Obsolete or Under Obsolescence
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
B SCANT.UPD
TDO Source
Readback
BSCAN.
BSCAN.
Register
Bypass
DOUT
TDO1
TDO2
Data
DR
DR
XC4000E and XC4000X Series Field Programmable Gate Arrays
—
User Logic
User Logic
Pin/Logic
Pin/Logic
Disabled
I/O Data
X6075
Source
DR
—
—
Configuration
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. XC4000
Series devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each con-
figuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACT step
development system translates the design into a netlist file.
It automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
can be used as an output. The XACT step development sys-
tem does not use these resources unless they are explicitly
specified in the design entry. This is done by placing a spe-
cial pad symbol called MD2, MD1, or MD0 instead of the
input or output pad symbol.
In XC4000 Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular configuration mode. Therefore, for the most com-
mon configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 k .) After configuration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specified in the design. A pull-down resistor value
of 4.7 k is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
Figure 43: Boundary Scan Schematic Example
TMS
operation
TCK
TDI
User Logic
From
of
Optional
TDI
TMS
TCK
TDO1
TDO2
the
BSCAN
IBUF
internal
DRCK
SEL1
SEL2
IDLE
TDO
blocks
To User
Logic
To User
Logic
TDO
X2675
and
6-45
their
6