XC4020E-2PG223I Xilinx Inc, XC4020E-2PG223I Datasheet - Page 35

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XC4020E-2PG223I

Manufacturer Part Number
XC4020E-2PG223I
Description
IC FPGA I-TEMP 5V 2SPD 223-CPGA
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4020E-2PG223I

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
192
Number Of Gates
20000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
223-BCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
The top and bottom Global Early buffers are about 1 ns
slower clock to out than the left and right Global Early buff-
ers.
The Global Early buffers can be driven by either semi-ded-
icated pads or internal logic. They share pads with the Glo-
bal Low-Skew buffers, so a single net can drive both global
buffers, as described above.
To use a Global Early buffer, place a BUFGE element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=T attribute or property
to direct that a BUFGE be placed in one of the two Global
Early buffers on the top edge of the device, or a LOC=TR to
indicate the Global Early buffer on the top edge of the
device, on the right.
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately de-coupled.
Typically, a 0.1 F capacitor connected between each Vcc
pin and the board’s Ground plane will provide adequate
de-coupling.
Output buffers capable of driving/sinking the specified 12
mA loads under specified worst-case conditions may be
capable of driving/sinking up to 10 times as much current
under best case conditions.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default) which
should be used where output rise and fall times are not
speed-critical.
May 14, 1999 (Version 1.6)
Figure
R
39. An independent matrix of Vcc and
Product Obsolete or Under Obsolescence
XC4000E and XC4000X Series Field Programmable Gate Arrays
Pin Descriptions
There are three types of pins in the XC4000 Series
devices:
• Permanently dedicated pins
• User I/O pins that can have special functions
• Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with a 50 k
pull-up resistor.
After configuration, if an IOB is unused it is configured as
an input with a 50 k - 100 k pull-up resistor.
XC4000 Series devices have no dedicated Reset input.
Any user I/O can be configured to drive the Global
Set/Reset net, GSR. See
for more information on GSR.
XC4000 Series devices have no Powerdown control input,
as
XC3000/XC2000 Powerdown control also 3-stated all of the
device
I/O pins. For XC4000 Series devices, use the global 3-state
net, GTS, instead. This net 3-states all outputs, but does
not place the device in low-power mode. See
Signals” on page 23
Device pins for XC4000 Series devices are described in
Table
seven configuration modes are summarized in
page
Figure 39: XC4000 Series Power Distribution
Vcc
the
58, in the “Configuration Timing” section.
16. Pin functions during configuration for each of the
XC3000
for more information on GTS.
and
GND
GND
“Global Set/Reset” on page 11
XC2000
families
Vcc
Logic
Power Grid
Ground and
Vcc Ring for
I/O Drivers
“IOB Output
Table 22 on
do.
X5422
- 100 k
6-39
The
6

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