XC4020E-3PG223I Xilinx Inc, XC4020E-3PG223I Datasheet - Page 45

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XC4020E-3PG223I

Manufacturer Part Number
XC4020E-3PG223I
Description
IC FPGA I-TEMP 5V 3SPD 223-CPGA
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4020E-3PG223I

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
192
Number Of Gates
20000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
223-BCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4020E-3PG223I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 20: XC4000E Program Data
Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Table 21: XC4000EX/XL Program Data
Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in
error is detected during the loading of the FPGA, the con-
May 14, 1999 (Version 1.6)
Max Logic Gates
CLBs
(Row x Col.)
IOBs
Flip-Flops
Bits per Frame
Frames
Program Data
PROM Size
(bits)
Max Logic
Gates
CLBs
(Row x
Column)
IOBs
Flip-Flops
Bits per
Frame
Frames
Program Data
PROM Size
(bits)
Notes: 1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.
Device
Device
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading “ones” at the beginning of the header.
R
XC4002XL XC4005 XC4010 XC4013 XC4020 XC4028 XC4036
61,052
61,104
(8 x 8)
2,000
256
133
459
64
64
XC4003E
(10 x 10)
53,936
53,984
3,000
Product Obsolete or Under Obsolescence
100
360
126
428
80
(14 x 14)
151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940
151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992
5,000
196
112
616
205
741
Table
XC4005E
(20 x 20)
(14 x 14)
10,000
94,960
95,008
1,120
1,023
5,000
400
160
277
XC4000E and XC4000X Series Field Programmable Gate Arrays
196
112
616
166
572
19. If a frame data
(24 x 24)
13,000
1,536
1,211
576
192
325
XC4006E
(16 x 16)
119,792
119,840
6,000
256
128
768
186
644
(28 x 28)
20,000
2,016
1,399
784
224
373
XC4008E
(18 x 18)
147,504
147,552
8,000
(32 x 32)
324
144
936
206
716
28,000
figuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in
icant bits of the 16-bit code. A change in the checksum indi-
cates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB out-
puts should not be included (Read Capture option not
1,024
2,560
1,587
256
421
Figure
(36 x 36)
36,000
XC4010E
1,296
3,168
1,775
(20 x 20)
45. The checksum consists of the 11 most signif-
178,096
178,144
288
469
10,000
1,120
400
160
226
788
(40 x 40)
XC4044
44,000
1,600
3,840
1,963
320
517
XC4013E
(24 x 24)
247,920
247,968
13,000
1,536
576
192
266
932
(44 x 44)
XC4052
52,000
1,936
4,576
2,151
352
565
XC4020E
(28 x 28)
329,264
329,312
20,000
2,016
1,076
784
224
306
(48 x 48)
XC4062
62,000
2,304
5,376
2,339
384
613
XC4025E
(32 x 32)
422,128
422,176
25,000
1,024
2,560
1,220
(56 x 56)
XC4085
256
346
85,000
3,136
7,168
2,715
448
709
6-49
6

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