XC4020E-3PG223I Xilinx Inc, XC4020E-3PG223I Datasheet - Page 7

• Manufacturer Part Number: XC4020E-3PG223I
• Description: IC FPGA I-TEMP 5V 3SPD 223-CPGA
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4020E-3PG223I

• Number Of Logic Elements/cells: 1862
• Number Of Labs/clbs: 784
• Total Ram Bits: 25088
• Number Of I /o: 192
• Number Of Gates: 20000
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 223-BCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Set/Reset
An asynchronous storage element input (SR) can be con-
figured as either set or reset. This configuration option
determines the state in which each flip-flop becomes oper-
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three
set/reset functions for any single flip-flop are controlled by
the same configuration data bit.
The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.
The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.
SR is active High. It is not invertible within the CLB.
Global Set/Reset
A separate Global Set/Reset line (not shown in
sets or clears each storage element during power-up,
re-configuration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.
Figure 2: Schematic Symbols for Global Set/Reset
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See
cific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program-
mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Set/Reset sig-
nal.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is driven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) block input. The flip-flops or latches drive
the XQ and YQ CLB outputs.
May 14, 1999 (Version 1.6)
PAD
R
IBUF
Product Obsolete or Under Obsolescence
GSR
GTS
CLK DONEIN
XC4000E and XC4000X Series Field Programmable Gate Arrays
STARTUP
Figure
Q1Q4
Q2
Q3
2.) A spe-
Figure
X5260
1)
Two fast feed-through paths are available, as shown in
Figure
YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used by
the automated router to repower internal signals.
Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4
in
DIN/H2, SR/H0, and EC). Any of these inputs can drive any
of the four internal control signals.
When the logic function is enabled, the four inputs are:
• EC — Enable Clock
• SR/H0 — Asynchronous Set/Reset or H function
• DIN/H2 — Direct In or H function generator Input 2
• H1 — H function generator Input 1.
When the memory function is enabled, the four inputs are:
• EC — Enable Clock
• WE — Write Enable
• D0 — Data Input to F and/or G function generator
• D1 — Data input to G function generator (16x1 and
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC4000 Series invites
pipelined designs. This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000X only) is called LDCE.
In XC4000 Series devices, the flip flops can be used as reg-
isters or shift registers without blocking the function gener-
ators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
The CLB setup time is specified between the function gen-
erator inputs and the clock input K. Therefore, the specified
CLB flip-flop setup time includes the delay through the
function generator.
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000/A/H families),
edge-triggered, and dual-port edge-triggered. Depending
on the selected mode, a single CLB can be configured as
either a 16x2, 32x1, or 16x1 bit array.
generator Input 0
16x2 modes) or 5th Address bit (32x1 mode).
Figure
1. A two-to-one multiplexer on each of the XQ and
1) into the four internal control signals (H1,
6-11
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