XC4036XL-3HQ208C Xilinx Inc, XC4036XL-3HQ208C Datasheet - Page 52
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XC4036XL-3HQ208C
Manufacturer Part Number
XC4036XL-3HQ208C
Description
IC FPGA C-TEMP 3.3V 3SPD 208HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4036XL-3HQ208C.pdf
(68 pages)
Specifications of XC4036XL-3HQ208C
Number Of Logic Elements/cells
3078
Number Of Labs/clbs
1296
Total Ram Bits
41472
Number Of I /o
160
Number Of Gates
36000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC4000E and XC4000X Series Field Programmable Gate Arrays
Readback Options
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with the bitstream generation
software.
Read Capture
When the Read Capture option is selected, the readback
data stream includes sampled values of CLB and IOB sig-
nals. The rising edge of RDBK.TRIG latches the inverted
values of the four CLB outputs, the IOB output flip-flops and
the input signals I1 and I2. Note that while the bits describ-
ing configuration (interconnect, function generators, and
RAM content) are not inverted, the CLB and IOB output sig-
nals are inverted.
When the Read Capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations.
If the RAM capability of the CLBs is used, RAM data are
available in readback, since they directly overwrite the F
and G function-table configuration of the CLB.
RDBK.TRIG is located in the lower-left corner of the device,
as shown in
Read Abort
When the Read Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the readback opera-
tion and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up to one
readback clock per configuration frame) may be required to
re-initialize the control logic. The status of readback is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If readback
must be inhibited for security reasons, the readback control
nets are simply not connected.
RDBK.CLK is located in the lower right chip corner, as
shown in
6-56
Figure 49: Readback Schematic Example
Figure
Figure
50.
50.
MD0
IF UNCONNECTED,
DEFAULT IS CCLK
READ_TRIGGER
IBUF
TRIG
CLK
READBACK
Violating the Maximum High and Low Time
Specification for the Readback Clock
The readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the follow-
ing frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the read-
back data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
are listed in
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
cation. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-cir-
cuit emulator.
Figure 50: READBACK Symbol in Graphical Editor
DATA
RIP
I/O
rdbk
Table
OBUF
PROGRAMMABLE
INTERCONNECT
READ_DATA
19,
I/O
Table 20
X1786
MD1
I/O
and
May 14, 1999 (Version 1.6)
Table
I/O
21.
rdclk
I/O
X1787
R