XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 57
XC5VFX30T-1FF665CES
Manufacturer Part Number
XC5VFX30T-1FF665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FF665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VFX30T-1FF665CES
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Dynamic Reconfiguration Ready Output - DRDY
Table 2-4: DCM Status Mapping to DO Bus (Continued)
When LOCKED is Low (during reset or the locking process), all the status signals are
deasserted Low.
The dynamic reconfiguration ready (DRDY) output pin provides the response to the DEN
signal for the DCM’s dynamic reconfiguration feature. Further information on the DRDY
pin is available in the dynamic reconfiguration section in the Virtex-5 FPGA Configuration
Guide.
DO[3]
DO[15:4]
DO Bit
CLKFB stopped
Not assigned
Status
www.xilinx.com
Asserted when the feedback clock is stopped (CLKFB
remains High or Low for one or more clock cycles). The
DO[3] CLKFB stopped status is asserted within six
CLKIN cycles after CLKFB is stopped. CLKFB stopped
will deassert within six CLKIN cycles when CLKFB
resumes after being stopped momentarily. An
occasionally skipped CLKFB does not affect the DCM
operation. However, stopping CLKFB for a long time
can result in the DCM losing LOCKED. When LOCKED
is lost, the DCM needs to be reset to resume operation.
When the DLL portion of the DCM is not used (for
example, when using CLKFX output only), the CLKFB
can be left unconnected. In this case, DO[3] is
deasserted.
Description
DCM Ports
57
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