AT94S40AL-25DGC Atmel, AT94S40AL-25DGC Datasheet

IC FPSLIC 40K GATE 25MHZ 256BGA

AT94S40AL-25DGC

Manufacturer Part Number
AT94S40AL-25DGC
Description
IC FPSLIC 40K GATE 25MHZ 256BGA
Manufacturer
Atmel
Series
FPSLIC®r
Datasheet

Specifications of AT94S40AL-25DGC

Core Type
8-bit AVR
Speed
16MHz
Interface
I²C, UART
Program Sram Bytes
20K-32K
Fpga Sram
18kb
Eeprom Size
1M x 8
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
2304
Fpga Gates
40K
Fpga Registers
2862
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
256-CABGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT94S40AL-25DGC
Manufacturer:
Atmel
Quantity:
10 000
Features
Multichip Module Containing Field Programmable System Level Integrated Circuit
(FPSLIC
512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
Field Programmable System Level Integrated Circuit (FPSLIC)
5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
Patented AVR Enhanced RISC Architecture
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
JTAG (IEEE Std. 1149.1 Compliant) Interface
AVR Fixed Peripherals
Support for FPGA Custom Peripherals
Up to 16 FPGA Supplied Internal Interrupts to AVR
Up to Four External Interrupts to AVR
8 Global FPGA Clocks
Multiple Oscillator Circuits
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save, and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
– Extensive On-chip Debug Support
– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
– Industry-standard 2-wire Serial Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly
– FPGA Macro Library of Custom Peripherals
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
Extensive Data and Instruction SRAM
On-chip from AVR Microcontroller Core to Support Cache Logic
Handheld Applications
Modes and Dual 8-, 9- or 10-bit PWM
Accessible to FPGA
®
) and Secure Configuration EEPROM Memory
®
Designs
®
Core and
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
2314E–FPSLI–6/05

Related parts for AT94S40AL-25DGC

AT94S40AL-25DGC Summary of contents

Page 1

Features • Multichip Module Containing Field Programmable System Level Integrated Circuit ® (FPSLIC ) and Secure Configuration EEPROM Memory • 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System Programming (ISP) • Field Programmable System Level ...

Page 2

... Yes Yes 2 Yes 3 Yes Yes @ 25 MHz 19 MIPS @ 40 MHz 30 MIPS 3.0 - 3.6V Table 1 combination of the popular AT94S10AL AT94S40AL 1 Mbit 1 Mbit 10K 40K 576 2304 4096 18432 846 2862 137 162 16 16 20K - 32K 20K - 32K 4K - 16K 4K - 16K Yes Yes ...

Page 3

... CISC microcontrollers at the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA configuration SRAM and AVR instruction code SRAM are automatically loaded at system power-up using Atmel’s in-system programmable AT17 Series EEPROM con- figuration memories, which are part of the AT94S Multi-chip Module (MCM). ...

Page 4

... Internal Architecture For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K FPSLIC datasheet and the AT17 Series Configuration Memory datasheet, available on the Atmel web site at http://www.atmel.com. This document only describes the differences between the AT94S Secure FPSLIC and the AT94K FPSLIC. ...

Page 5

Low. The system must provide a small pull-up current (1 k equiv- alent) for the cSDA line. The MESSAGE FORMAT for read and write instructions consists of the bytes shown in mat” on page ...

Page 6

Acknowledge Bit The Acknowledge (ACK) Bit shown in byte. The receiving Configurator can accept the byte by asserting a Low value on the cSDA line can refuse the byte by asserting (allowing the signal to be externally ...

Page 7

EEPROM Address Byte Order MSB LSB E16 1st 2nd 3rd 4th 5th 6th 7th 8th The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is followed ...

Page 8

Programming Summary: Write to Whole Device START SER_EN Low PAGE_COUNT 0 Send Start Condition BYTE_COUNT 0 Send Device Address ($A6) Yes Send MSB of (1) EEPROM Address Yes Middle Byte EEPROM Address Yes Send LSB of (1) EEPROM Address ...

Page 9

Programming Summary: Read from Whole Device START SER_EN Low Send Start Condition Send Device Address ($A6) Yes Middle Byte EEPROM Address Yes Send MSB of (1) EEPROM Address Yes Send LSB of (1) EEPROM Address Yes Send Start condition ...

Page 10

Data Byte LSB D0 D1 1st 2nd The organization of the Data Byte is shown above. Note that in this case, the Data Byte is clocked into the device LSB first and MSB last. 4.9.4 Writing Writing to the ...

Page 11

Reading Read instructions are initiated similarly to write instructions. However, with the R/W bit in the Device Address set to one. There are three variants of the read instruction: current address read, random read and sequential read. For all ...

Page 12

Sequential Read Sequential Reads follow either a Current Address Read or a Random Address Read. After the programmer receives a Data Byte, it may respond with an Acknowledge Bit. As long as the Con- figurator receives an Acknowledge Bit, ...

Page 13

... Read the Manufacturer’s Code and the Device Code. 2. Program the device. 3. Verify the device data. While Atmel’s Secure FPSLIC Configurators can be programmed from various sources (e.g., on- board microcontrollers or PLDs), the applications shown here are designed to facilitate users of our ATDH2225 Configurator Programming Cable. The typical system setup is shown in 2 ...

Page 14

Figure 4-3. RESET Note: Figure 4-4. Serial Data Timing Diagram cSCK t HD.STA t SU.STA cSDA cSDA AT94S Secure Family 14 ISP of the AT17LV512/010 in an AT94S FPSLIC Application AT94S RESET DATA0 (cSDA) CLK (cSCK) INIT (RESET/OE) M2 CON ...

Page 15

DC Characteristics V = 3.3V ± 10 -40°C - 85° Symbol Parameter V Supply Voltage CC I Supply Current CC I Input Leakage Current LL I Output Leakage Current LO V High-level Input Voltage ...

Page 16

LQFP 105 107 4.14 Security Bit Once the security bit is programmed, data will no longer output from the normal data pad. Once the fuse is set, any attempt to erase the fuse will ...

Page 17

Chip Erase Timing The entire device can be erased at once by writing to a specific address. This operation will erase the entire array. See Table 4-2. Symbol Tec Figure 4-5. SCL SDA 5. Packaging and Pin List information ...

Page 18

Table 5-3. AT94S Pin List AT94S05 96 FPGA I/O 144 FPGA I/O I/O1, GCK1 (A16) I/O1, GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19 I/O7 I/ I/O9, FCK1 I/O13, FCK1 I/O10 I/O11 ...

Page 19

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I I/O13 I/O14 I/O15 (A22) I/O16 (A23) I/O17 (A24) I/O18 (A25) I/O19 I/O20 2314E–FPSLI–6/05 AT94S10 AT94S40 ...

Page 20

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I I/O21 (A26) I/O22 (A27) I/O23 I/O24, FCK2 I/O36, FCK2 I/O25 I/O26 I/O27 (A28) I/O28 I/O29 I/O30 I/O31 (OTS) I/O47 (OTS) I/O32, GCK2 (A29) I/O48, GCK2 ...

Page 21

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O33, GCK3 I/O34 (HDC/TDI) I/O50 (HDC/TDI) I/O35 I/O36 SER_EN I/O38 (LDC/TDO) I/O54 (LDC/TDO I/O39 I/O40 NC NC I/O41 I/O42 I/O43 (TMS) I/O44 (TCK ...

Page 22

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I I/O45 I/O46 I/O47 (TD7) I/O71 (TD7) I/O48 (InitErr) RESET/OE I/O72 (InitErr) RESET/OE I/O49 (TD6) I/O73 (TD6) I/O50 (TD5) I/O74 (TD5) I/O51 I/O52 ...

Page 23

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O NC I/O53 (TD4) I/O54 (TD3) I/O55 I/O56 I/O57 I/O58 NC NC I/O59 (TD2) I/O60 (TD1) I/O61 I/O62 I/O63 (TD0) I/O64, GCK4 ...

Page 24

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O PD0 PD1 PE2 PD2 NC SER_EN PD3 PD4 PE3 CS0 SDA SCL PD5 PD6 PE4 PE5 PE6 PE7 (CHECK) PE7 (CHECK) PD7 INTP0 XTAL1 XTAL2 RX0 TX0 ...

Page 25

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O Testclock I/O97 (A0) I/O98, GCK7 (A1) I/O146, GCK7 (A1) I/O99 I/O100 NC NC I/O101 (CS1, A2) I/O149 (CS1, A2) I/O102 (A3) I/O104 NC I/O103 ...

Page 26

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O107 (A4) I/O108 (A5 I/O109 I/O110 I/O111 (A6) I/O112 (A7) I/O113 (A8) I/O114 (A9) I/O115 I/O116 NC NC I/O117 (A10) I/O175 (A10) I/O118 (A11) I/O176 ...

Page 27

Table 5-3. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I I/O119 I/O120 NC NC I/O121 I/O122 I/O123 (A12) I/O124 (A13 I/O125 I/O126 I/O127 (A14) I/O128, GCK8 (A15) I/O192, GCK8 (A15) Note: 1. LQ144 ...

Page 28

... LQ144 18, 54, 90, 128 Note: 1. For power rail support for product migration to lower-power devices, refer to the “Designing in Split Power Supply Support for AT94KAL/AX and AT94SAL/AX Devices” application note (doc2308.pdf), available on the Atmel web site, at http://www.atmel.com/dyn/products/app_notes.asp?family_id=627. 6. Thermal Coefficient Table Package Style ...

Page 29

... Chip Array Ball Grid Array Package (CABGA) 144L1 144-lead, Low Profile Plastic Gull Wing Quad Flat Package (LQFP) 2314E–FPSLI–6/05 Ordering Code AT94S05AL-25DGC AT94S05AL-25BQC AT94S05AL-25DGI AT94S05AL-25BQI AT94S10AL-25DGC AT94S10AL-25BQC AT94S10AL-25DGI AT94S10AL-25BQI AT94S40AL-25DGC AT94S40AL-25DGI Package Type AT94S Secure Family Package Operation Range 256ZA Commercial 144L1 ( 256ZA Industrial 144L1 ...

Page 30

Packaging Information 8.1 256ZA – CABGA A1 Ball Pad Corner Top View 1.00 REF Bottom View (256 SOLDER BALLS) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing ...

Page 31

LQFP Top View Side View 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. Notes: 2. The top package body size may be smaller ...

Page 32

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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