FMS7401LEN14 Fairchild Semiconductor, FMS7401LEN14 Datasheet
FMS7401LEN14
Specifications of FMS7401LEN14
FMS7401LEN14_NL
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FMS7401LEN14 Summary of contents
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FMS7401L Digital Power Controller General Description The FMS7401L is a Digital Power Controller designed for applications requiring ease of digital based control over ana- log based implementations. The FMS7401L is an ideal solu- tion to implement ballast control, motor control ...
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FMS7401L Block Diagram G7/AIN4/ A OUT Uncommitted Amplifier _ G6/- Vcc + REF G3/AIN1 G2/AIN2 G1/AIN3/ ADSTROBE Autozero Amplifier _ SR_GND x16 G4/AIN0 + Unit Gain A NC/GND OUT Figure 1. FMS7401L Block and Connection Diagram Pin Configurations ...
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PRODUCT SPECIFICATION FMS7401L Pin Definitions Pin Number 8-Pin 14-Pin PDIP PDIP SOIC SOIC TSSOP TSSOP Pin Name G4/AIN0 GND G2/AIN2 G1/AIN3/ ADSTROBE G3/AIN1 6 8 ...
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FMS7401L Table of Contents FMS7401L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PRODUCT SPECIFICATION 10 8-Bit Microcontroller Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FMS7401L List of Figures Figure 1. FMS7401L Block and Connection Diagram Figure 2. BOR and POR Circuit Relationship Diagram Figure 3. Internal Clock Scheme . . . . . . . . . . . . . . . . ...
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PRODUCT SPECIFICATION List of Tables Table 1. Default Register States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FMS7401L 1 Reset Circuit The reset circuit in the FMS7401L contains four input conditions that trigger a main system reset. When the main system reset is triggered, a sequence of events occur defaulting all memory mapped registers (including the initialization ...
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PRODUCT SPECIFICATION The BOR circuit should be used in situations when Vcc rises and falls slowly and in situations when Vcc does not fall to 0V before rising back to the device’s normal operating range. The BOR circuit can be ...
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FMS7401L 2 Clock Circuit The FMS7401L may be clocked using its internal oscillator circuit or using an external digital clock signal. The desired clock source is selectable by the CMODE bit of the Initialization Register 1. and the desired clock ...
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PRODUCT SPECIFICATION The FS[1:0] bits of the PSCALE register changed by software at any time; however, if the PWM Timer 1 circuit is in run mode the FS[1:0] value will not change the F output frequency until after the PWM ...
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FMS7401L Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers 1. ...
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PRODUCT SPECIFICATION 3 Power Saving Modes The FMS7401L has both Halt and Idle power saving modes. Each mode is controlled by software and offers the advantage of reducing the total current consumption of the device in an application. For all ...
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FMS7401L enabled, it must complete the lock phase before software may enable the use of the outputs to clock any of the device circuits. Therefore, upon exiting Halt Mode software must wait the T frequency and in phase. 1. Initially, ...
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PRODUCT SPECIFICATION 1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL ...
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FMS7401L 4 ADC Circuit The Analog-to-Digital Converter (ADC) Circuit extends the features of the FMS7401L by offering a 5-channel 8-bit ADC. The ADC may be programmed to convert voltages on any of the eight inputs of the analog mux, where ...
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PRODUCT SPECIFICATION Vcc ENIS G3/AIN1 G2/AIN2 G1/AIN3 ACH5 GND Autozero SR_GND Amplifier _ x16 + G4/AIN0 GAIN COMPSEL G7/AIN4/A OUT _ G6/- REF 4.1.1 ADCNTRL1 Register The ADCNTRL1 is an 8-bit memory map register used to configure ...
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FMS7401L Bit 6 of the ADCNTRL1 register is the ADC’s microcontroller hardware interrupt enabled (AINTEN) bit. If set, hardware interrupts (ADCI) are enabled and triggered by the APND pending flag. interrupt will continue to execute software’s ADC interrupt service routine ...
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PRODUCT SPECIFICATION Table 5. ADCNTRL1 Register Bit Definitions Bit 7 Bit 6 Bit 5 APND AINTEN ASTART Bit Description APND (0) ADC’s pending flag is cleared. (1) ADC’s pending flag is triggered. AINTEN (0) Disables ADC hardware interrupts. (1) Enables ...
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FMS7401L options must be prepared prior to setting the ENDAS bit. Refer to the following additional details. The ADSTROBE signal is generated by the PWM Timer 1 circuit and is configured using its T1CMPB and T1RA registers. Refer to the ...
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PRODUCT SPECIFICATION Table 7. ADCNTRL2 Register Bit Definitions Bit 7 Bit 6 Bit 5 REFBY2 COMPSEL ENAMP Bit Description REFBY2 Used to divide the reference clock for the PLL and digital filter of the Programmable Comparator circuit. Refer to the ...
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FMS7401L this information because the APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion completion delay may occur when the F 4.2.1 Analog Input Voltage and its 8-bit Digital Result The relationship between the 8-bit ...
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PRODUCT SPECIFICATION accuracy. However, if the internal oscillator is trimmed to its upper F ASPEED[1:0]=1 divided factor must be selected to yield selected by setting the ASPEED[1:0]>1. 4.3 Autozero Amplifier The GAIN bit of the ADCNTRL2 register ...
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FMS7401L Control Voltage 1. Refer to the Electrical Characteristics section of the datasheet for details. 2. Refer to the PWM Timer 1 Circuit section of the datasheet for details regarding the ADSTROBE signal configuration. 3. Refer to Table 30 of ...
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PRODUCT SPECIFICATION 5 Programmable Comparator Circuit The Programmable Comparator circuit is an analog comparator whose outputs may be monitored by software or fed into a dig- ital delay filter used to disable the PWM Timer 1 circuit or its PWM ...
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FMS7401L Bits 7-2 (CL[5:0]) is the comparator voltage threshold level selection bits of the Comparator Control (COMP) register. The CL bits may be programmed to select one of the voltage threshold levels as the inverting input of the analog comparator. ...
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PRODUCT SPECIFICATION Table 9. Programmable Comparator Lower Voltage Reference V Level CL[5] CL[ ...
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FMS7401L Table 10. Programmable Comparator Upper Voltage Reference V Level CL[5] CL[ ...
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PRODUCT SPECIFICATION Bit 6 of the ADCNTRL2 register is the Programmable Comparator non-inverting input selection (COMPSEL) bit. COMPSEL=0, the non-inverting input of the Programmable Comparator is the G4/AIN0 device pin. If COMPSEL=1, the non- inverting input of the Programmable Comparator ...
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FMS7401L 5.3 Digital Delay Filter with PWMOFF Output The Programmable Comparator’s output (C signal toggles from when the external input (G4/AIN0 or G2/AIN2) voltage is higher than the programmed voltage threshold or Uncommitted Amplifier output (A the ...
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PRODUCT SPECIFICATION Table 11. Digital Delay (DDELAY) Register Bit Definitions Bit 7 Bit 6 Bit 5 COMPEN PWMINT EPWM Bit Description COMPEN (0) Disable the Programmable Comparator circuit. (1) Enable the Programmable Comparator circuit. PWMINT (0) The input of the ...
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FMS7401L 6 PWM Timer 1 Circuit The Pulse Width Modulation (PWM) Timer 1 circuit, a programmable 12-bit PWM timer with a 3-bit prescaler can be config- ured to operate in both PWM and Input Capture Modes. In PWM Mode, the ...
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PRODUCT SPECIFICATION Bit 4 of the PSCALE register is the frequency selection (FSEL) bit for the Timer 1 circuit. FSEL is used to select between the slow or high frequency options, ultimately selecting the F If FSEL=0, the slow frequency ...
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FMS7401L Table 14. Timer 1 Prescale Selection (PS) Bits PS[2] PS[ 6.1.2 PWM Cycle Configuration Registers The PWM Timer 1 circuit has three 12-bit (T1CMPA, T1CMPB, T1RA) and one 5-bit (DTIME) configuration ...
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PRODUCT SPECIFICATION Table 15. Dead Time (DTIME) Register Bit Definitions Bit 7 Bit 6 Bit DT[4:0] Dead Time Delay (T 0x00 No Dead Time Delay 0x01 – 0x1F (1/F T1CLK 6.1.3 Timer 1 Control Register The Timer ...
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FMS7401L pletes, will dictate the device’s I/O attribute for the next PWM cycle. When reading the T1BOUT, the value reported will be the last value written by software and may not necessarily reflect the device’s I/O attribute for the current ...
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PRODUCT SPECIFICATION Table 16. Timer 1 Control (T1CNTRL) Register Bit Definitions Bit 7 Bit 6 Bit 5 T1C3 T1C2 T1C1 Bit Description T1C3 Timer 1 Mode Configuration Bit. Refer to T1C2 Timer 1 Mode Configuration Bit. Refer to T1C1 Timer ...
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FMS7401L The PWM Timer 1 can be programmed to toggle one or both PWM output signals (T1HS1 and T1HS2) to support a variety of output configurations (half bridge, full bridge, half-bridge driver and are enabled by programming the T1C1 and ...
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PRODUCT SPECIFICATION T1CMPB [11:0] Clock F T1CLK Fin Fout DIVIDER PS2 PS1 PS0 PSCALE Figure 12. Example PWM Output Signals a) and b) a) T1HS1 T1HS2 0xFFF T1RA T1CMPB T1CMPA 0x00 T1HS1 T1HS2 T DT ADSTROBE Sample ...
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FMS7401L 6.3 Input Capture Mode When the PWM Timer 1 circuit is configured in Input Capture Mode, the T1HS2 signal is used as an input of the Timer 1 circuit instead of an output as in PWM Mode. The G5/T1HS2 ...
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PRODUCT SPECIFICATION 7 Timer 0 Circuit Timer 0’s main circuit is a 12-bit free running up-counter whose clock source is the main system instruction clock (F main counter may be used to generate microcontroller hardware interrupts and serve as a ...
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FMS7401L issue a system reset unless the feature is enabled by the Watchdog Enable (WDEN) bit of the Initialization Register 1. WDEN bit can only be set while the device is in programming mode. always power-up enabled. Software cannot disable ...
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PRODUCT SPECIFICATION 8 I/O Ports The eight I/O pins (six on the 8-pin package option) are bi-directional (see vidually configured by software to operate as high-impedance inputs, as inputs with weak pull-up push-pull outputs. The operating state is ...
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PRODUCT SPECIFICATION 9 Multi-input Wakeup Circuit The Multi-input Wakeup (MIW) circuit may be used to wake the device from either Halt or Idle Mode generate flags for software monitoring and microcontroller hardware interrupts by any one or all I/O ports ...
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FMS7401L The MIW circuit can be used with the I/O ports configured as both an input and output. The MIW configuration and function is the same for both I/O configurations. However, when using the MIW circuit to wake the device ...
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PRODUCT SPECIFICATION 10 8-Bit Microcontroller Core The FMS7401L’s 8-bit microcontroller core is specifically designed for low cost applications involving bit manipulation, shift- ing and block encryption based on a modified Harvard architecture meaning peripheral, I/O and RAM locations ...
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FMS7401L 10.1.1 Accumulator (A) The Accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manipulations. 10.1.2 X-Pointer (X) The X-Pointer register allows for an 11-bit indexing value to be added ...
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PRODUCT SPECIFICATION Carry/Borrow (C) The carry flag is set if the arithmetic logic unit (ALU) performs a carry or borrows during an arithmetic operation and by its special inherent instructions—set carry (SC), load carry (LDC) and invert carry (INVC). The ...
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PRODUCT SPECIFICATION 10.1.6 Interrupt Handling When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the program counter, PC) is pushed onto the stack, the global interrupt (G) mask of the status ...
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PRODUCT SPECIFICATION 10.2 Addressing Modes The microcontroller core has seven instruction addressing modes: inherent, immediate, direct, indirect, indexed, absolute jump and relative jump (see Table 24). Inherent The inherent addressing mode instructions either have no operand associated or the contents ...
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FMS7401L Table 24. Instruction Addressing Modes Instruction Immediate ADC A, # ADD A, # AND SUBC A, # XOR A, # CLR INC DEC IFEQ IFGT ...
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PRODUCT SPECIFICATION Table 25. Instruction Cycles and Bytes Mnemonic Operand Bytes ADC A, [X] 1 ADC A, [#,X] 2 ADC ADC ADD A, [X] 1 ADD A, [#,X] 2 ADD ADD ...
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FMS7401L 1. The FMS7401L’s normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program residing in the code EEPROM memory. During this time, the code EEPROM memory may only be ...
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PRODUCT SPECIFICATION 11 Device Memory The FMS7401L has 64 bytes of SRAM and 64 bytes of EEPROM (data EEPROM) available for data storage. It also has 1K Byte of EEPROM (code EEPROM) memory for program storage. During the device’s normal ...
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FMS7401L prior to leaving the factory with the appropriate calibration value and with the ports configured as tri-state inputs. In program- ming mode, the default port configuration may be changed; however, be sure to maintain the factory current source calibration ...
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PRODUCT SPECIFICATION Table 29. T1HS1 (G0) and T1HS2 (G5) Default Configuration T1HS_DIR T1HS2_LEV T1HS1_LEV REV. 1.0.3 1/24/05 0 T1HS1 and T1HS2 tri-state inputs 1 ...
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FMS7401L 11.2 Memory Map All I/O ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the memory space. Table 30. Memory Mapped Registers Address Memory Space 0x00 – 0x3F Data 0x40 – 0x7F ...
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PRODUCT SPECIFICATION Table 31. Memory Mapped Registers and their Register Bit Definitions 10 Address Name Bit7 0x9D ADATA 8-bit digital value of ADC conversion 0x9F ADCNTRL1 APND 0xA0 ADCNTRL2 REFBY2 0xA2 DDELAY COMPEN 0xA4 PSCALE PLLEN 0xA5 DTIME X 0xA6 ...
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FMS7401L 12 In-circuit Programming Specification The FMS7401L supports in-circuit programming of all internal memory mapped registers including the data EEPROM, code EEPROM, and initialization registers. In-circuit programming consists of a 4-wire serial interface used to place the device in pro- ...
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PRODUCT SPECIFICATION The opcode must be shifted in after Vcc settles to its nominal voltage level and before the system reset sequence (T pletes. Otherwise, the device will begin with its normal operation executing the instruction program residing in the ...
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FMS7401L between the device and external programmer hardware. The device sets SHIFT_OUT low during a page-write command by the time the external programmer has issued the second rising edge of CLOCK informing the programmer that the memory write is in ...
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PRODUCT SPECIFICATION ...
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FMS7401L 12.2.4 Program Memory Erase The external programmer may erase the entire code EEPROM memory array using two special program erase byte write commands. This special erase option may also be used to unlock memory protected (WDIS/RDIS=1) devices without compromising ...
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PRODUCT SPECIFICATION 13 Electrical Characteristics Absolute Maximum Ratings Parameter Ambient Storage Temperature Input Voltage Vcc Input Voltage Lead Temperature (10s max) Electrostatic Discharge on all pins Internal Voltage Regulator output current Operating Conditions Relative Humidity (non-condensing) EEPROM write limits REV. ...
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FMS7401L 13.1 FMS7401L (2.7V to 3.6V) DC Electrical Characteristics All measurements are valid for T =+25°C unless otherwise stated. A Symbol Parameter 1 I Active Supply Current CC (without data EEPROM writes in progress) Active Supply Current (with data EEPROM ...
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PRODUCT SPECIFICATION AC Electrical Characteristics All measurements are valid for T =+25°C unless otherwise stated. A Symbol Parameter 5 F Internal oscillator frequency OSC (factory trim set-point) ∆ckv Internal oscillator frequency voltage variation ∆ckt Internal oscillator frequency temperature variation F ...
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FMS7401L ADC Electrical Characteristics All measurements are valid for T =+25°C unless otherwise stated. A Parameter 3 ADC Integral Non Linearity (INL) Best Fit ADC Differential Non 3 Linearity (DNL) 3 ADC Conversion Time 3 Internal Voltage Reference (V ) ...
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PRODUCT SPECIFICATION Figure 22. Internal Oscillator Frequency (F 2.004 2.002 2.000 1.998 1.996 1.994 1.992 1.990 -40 Figure 23. Icc Active vs. Temperature (no PLL or data EEPROM writes) 900 850 800 750 700 650 600 -40 REV. 1.0.3 1/24/05 ...
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FMS7401L Figure 24. Icc Active vs. Temperature (no PLL, with data EEPROM writes) 1100 1050 1000 950 900 850 800 750 700 -40 Figure 25. Icc Active vs. Temperature (with PLL, no data EEPROM writes) 8.5 8.0 7.5 7.0 6.5 ...
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PRODUCT SPECIFICATION 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40 Figure 27. Idle Current vs. Temperature (no PLL) 210 200 190 180 170 160 150 -40 REV. 1.0.3 1/24/05 Figure 26. Halt Current vs. Temperature HALT ...
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FMS7401L Figure 28. Idle Current vs. Temperature (with PLL) 1.70 1.60 1.50 1.40 1.30 1.20 -40 2.5 2.0 1.5 1.0 0.5 0 Idle Current vs. Temperature (with PLL Temperature (°C) Figure 29 ...
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PRODUCT SPECIFICATION 2.5 2.0 1.5 1.0 0.5 0.0 2 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 REV. 1.0.3 1/24/05 Figure 30 25°C (G0 25° (G0, ...
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FMS7401L 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 2.75 2.74 2.74 2.73 2.73 2.72 2.72 2.71 2.71 2.70 -40 73 Figure 32 25°C (G0 25° ...
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PRODUCT SPECIFICATION Figure 34. Programmable Comparator Voltage Level vs. Temperature 2.5 2.0 1.5 1.0 0.5 0.0 -40 1.222 1.22 1.218 1.216 1.214 1.212 1.21 1.208 1.206 1.204 1.202 -40 REV. 1.0.3 1/24/05 Programmable Comparator Voltage Level vs. Temperature 0 25 ...
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FMS7401L Figure 36. Current Source (I 1040 1030 1020 1010 1000 990 980 970 960 950 940 -40 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 - vs. Temperature SRC Current Source (I ) vs. Temperature SCR ...
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PRODUCT SPECIFICATION 1. I Active current is dependent on the program code and number of active circuits. The I CC Timer 1, Timer 0, ADC, Uncommitted Amplifier, and Programmable Comparator circuits all active. 2. Refer to the Clock Circuit section ...
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... FMS7401L Ordering Information FSID Package FMS7401LEN PDIP8 FMS7401LVN PDIP8 FMS7401LEN14 PDIP14 FMS7401LVN14 PDIP14 FMS7401LEM8X SOIC8 FMS7401LEMX SOIC14 FMS7401LEMT8X TSSOP8 FMS7401LEMTX TSSOP14 77 Supply Voltage Temperature Range 2.7V to 3.6V -40°C to 85°C 2.7V to 3.6V -40°C to 125°C 2.7V to 3.6V -40°C to 85°C 2.7V to 3.6V -40° ...
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PRODUCT SPECIFICATION †† Physical Dimensions 8-Pin PDIP 0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128) 95° ±5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 14-Pin PDIP 14 PIN NO. 1 IDENT 1 0.092 DIA ...
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PRODUCT SPECIFICATION †† Physical Dimensions 8-Pin SOIC 0.150 - 0.157 (3.810 - 3.988) 0.010 - 0.020 x 45¡ (0.254 - 0.508) 0.004 0.0075 - 0.0098 (0.102) (0.190 - 0.249) All lead tips Typ. All Leads 14-Pin SOIC 0.150 - 0.157 ...
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FMS7401L †† Physical Dimensions 8-Pin TSSOP 0.246 - 0.256 (6.25 - 6.5) 0.123 - 0.128 (3.13 - 3.30) 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 14-Pin TSSOP 6.4 ...
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... NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems ...