PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 304
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Table 17: GPIO Interrupt Registers for the FIFO Queues (One for each FIFO Queue)
Table 18: GPIO Module Status Register for all 12 Timestamp Units
PNX15XX_PNX952X_SER_N_4
Product data sheet
3
2
1
0
Offset 0x10,4FE0
31:24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
Bit
Bit
Symbol
INT_OE_SET
FIFO_OE_SET
BUF2_RDY_SET
BUF1_RDY_SET
Symbol
Unused
INT_OE_11
INT_OE_10
INT_OE_9
INT_OE_8
INT_OE_7
INT_OE_6
INT_OE_5
INT_OE_4
INT_OE_3
INT_OE_2
INT_OE_1
INT_OE_0
DATA_VALID_11
DATA_VALID_10
DATA_VALID_9
DATA_VALID_8
DATA_VALID_7
DATA_VALID_6
4.12 GPIO Module Status Register for all 12 Timestamp Units
INT_STATUS4
Acces
s
W
W
W
W
Acces
s
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Value
0
0
0
0
Value
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
Active high internal overrun error interrupt set for queue <0-3>.
Active high FIFO overrun error interrupt set for queue <0-3>.
Active high Buffer 2 ready interrupt set for queue <0-3>.
Active high Buffer 1 ready interrupt set for queue <0-3>.
Description
Internal overrun error in TSU
read by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 10. Data in TSU overwritten before
read by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 9. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 8. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 7. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 6. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 5. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 4. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 3. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 2. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 1. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Internal overrun error in TSU 0. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
Data in TSU 11 is ready to be read.
Data in TSU 10 is ready to be read.
Data in TSU 9 is ready to be read.
Data in TSU 8 is ready to be read.
Data in TSU 7 is ready to be read.
Data in TSU 6 is ready to be read.
Chapter 8: General Purpose Input Output Pins
PNX15xx/952x Series
a
11. Data in TSU overwritten before
© NXP B.V. 2007. All rights reserved.
8-304
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