PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 218
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Philips Semiconductors
Volume 1 of 1
Table 10: Examples of I
PNX15XX_SER_3
Product data sheet
Size
16 kilobytes
32 kilobytes
64 kilobytes
Device
ATMEL 24C128
ATMEL 24C256
ATMEL 24C512
4.2 The Boot Commands and The Endian Mode
4.3 Details on I
2
C EEPROM Devices
When writing to an MMIO register address, there is no endian mode issue. The msbit
of the word ‘V’
SDRAM address there is an endian mode issue. Depending on the current endian
mode
DRAM gate
To retrieve the boot script, the Boot module performs the following I
The interpretation of this sequence by 2048 bytes or smaller EEPROMs is:
Hence, for a 2048-byte or smaller EEPROM, the boot image must start at byte 1.
The interpretation of this sequence by 4096 bytes or larger EEPROMs is:
Hence, for a 4096-byte or larger EEPROM, the boot image must start at byte 0.
•
•
•
•
•
•
•
•
In little-endian mode, the MSB of ‘V’ (or the last read EEPROM byte of the word),
end up in memory byte address ‘A+3’ and LSB (or first read EEPROM byte), end
up at the byte address ‘a’.
In big-endian mode, the MSB of ‘V’ (or last read EEPROM byte), end up at the
byte address ‘A’ and the LSB (or first read EEPROM byte), end up at the byte
address ‘A+3’.
START, 10100000, wait-for-ack, 00000000, wait-for-ack, 00000000, wait-for-ack,
STOP
START, 10100001, wait-for-ack, <accept data byte, send ACK or STOP if done>.
Write a byte value 0 to address 0 (setting the next address-pointer to byte
address 1).
Read, starting from address 1.
Write a 0 byte-long sequence to address 0 (setting next address pointer to byte
address 0).
Read, starting from address 0.
(Section 4. on page
Write Protection
Coverage
Full Array
Full Array
Full Array
(Section 2.3 on page
2
(Table
C Operation
Rev. 3 — 17 March 2006
2) end up as the msbit of the MMIO register. When writing to an
3-8), 32-bit words get written to memory through the DCS
Address Protocol
2 bytes
2 bytes
2 bytes
3-4) in one of these two ways:
Comment
Tested
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 6: Boot Module
2
C transactions:
6-15
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