PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 466
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Philips Semiconductors
Volume 1 of 1
2. Functional Description
Table 1: Module signal pins
PNX15XX_SER_3
Product data sheet
Signal
clk_fgpo
fgpo_rec_sync
fgpo_buf_sync
fgpo_start
or
fgpo_rec_start
Type
input
input
input
output
Description
From Clock Module. External FGPO clock on VDO_C2 pin is connected to the Clock Module.
FGPO data and control signals are output at each rising edge on clk_fgpo. Use the PNX15xx
Series Clock Module to change clk_fgpo characteristics.
From External PAD.
In external record/message sync mode a programmable transition on this pin will trigger the
output of a record or message after a synchronization delay of 4 FGPO clock cycles. If the
transition occurs before the FGPO has finished the output of a previous record or message,
the transition will be ignored.
From External PAD.
In external buffer sync mode a programmable transition on this pin will start a new buffer after
a synchronization delay of 4 FGPO clock cycles. If the transition occurs before the FGPO has
finished the current buffer, the transition will be ignored.
To External PAD VDO_D[32] via Output Router.
Message Passing Mode:
A positive pulse output on this pin indicates the start of a message. The pulse may be
programmed to occur one clock before or at the same clock with the first valid data sample.
Record Mode:
A positive pulse output on this pin indicates the start of a record. The pulse may be
programmed to occur one clock before or at the same clock with the first valid data sample
or
A positive pulse lasting as long as valid data samples are output.
Rev. 3 — 17 March 2006
Chapter 13: FGPO: Fast General Purpose Output
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
13-5
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