PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 480
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Table 3: Fast general purpose output (FGPO)
PNX15XX_SER_3
Product data sheet
Bit
1
0
Offset 0x07,1004
31:2
1:0
Offset 0x07,1008
31:2
1:0
Offset 0x07,100C
31:24
23:0
Offset 0x07,1010
31:24
23:0
Offset 0x07,1014
31:2
Symbol
TSTAMP_SELECT
VAR_LENGTH
BASE1
Reserved
BASE2
Reserved
Reserved
SIZE
Reserved
REC_SIZE
STRIDE
FGPO_BASE1
FGPO_BASE2
FGPO_SIZE
FGPO_REC_SIZE
FGPO_STRIDE
Acces
s
R/W
R/W
R/W
R
R/W
R
R
R/W
R
R/W
R/W
Value
0
0
0
0
0
0
0
0
0
0
0
…Continued
Rev. 3 — 17 March 2006
Description
0 = The REC_SYNC and BUF_SYNC fields control record/message
sync and buffer sync events.
1 = Overrides BUF_SYNC to “No Sync mode: 000”, REC_SYNC
field is ignored. Causes the FGPO to read an 8-byte record/
message header where the first 4-bytes contains the 32-bit
timestamp word. Record/message will start when the internal
timestamp matches the timestamp in the header.
Note: The length of the header (8 bytes) IS NOT included in the
record/message size in FGPO_SIZE register but IS included in the
stride (FGPO_STRIDE register).
0 = The length of each record/message is contained in the
FGPO_REC_SIZE register.
1 =Causes the FGPO to read an 8-byte record/message header
where the second 4-bytes contains the 32-bit record/message
length word.
Note: The length of the header (8 bytes) IS NOT included in the
record/message size in FGPO_SIZE register but IS included in the
stride (FGPO_STRIDE register).
32-bit word aligned address pointing to Buffer 1 base.
Always 0.
32-bit word aligned address pointing to Buffer 2 base.
Always 0.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages per buffer. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of samples per record/message. Range: 2 to 2
Address stride between records/messages
Record mode:
The value read from the header overrides the contents of the
FGPO_REC_SIZE register.
Message mode:
If the message length read from the header is greater than the
value in the FGPO_REC_SIZE register then the message is
truncated to FGPO_REC_SIZE samples.
Chapter 13: FGPO: Fast General Purpose Output
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
24
24
-1
-1
13-19
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