PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 632
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Table 8: Registers Description
Table 9: Destination Address Base
PNX15XX_SER_3
Product data sheet
Bit
23:16
15:8
7:0
Bit
Offset 0x04 F404
31:29
28:24
23:16
15:8
7:0
Symbol
Off[22:16]
Off[15:8]
Off[7:0]
Symbol
Swap[2:0]
Reserved
Off[22:16]
Off[15:8]
Off[7:0]
Destination Address Base
This register specifies the offset for pixel (0,0) of a source bitmap for XY to Linear
conversion of addresses.
This register is interpreted as a byte address. The lower three bits of this register
always read 0, regardless of the value written. This implies that the source base
address must be aligned to a 64-bit boundary.
Under many circumstances, this register will be initialized to the proper offset and
then changed only for special effects.
This register specifies the offset for pixel (0,0) of a destination bitmap for XY to Linear
conversion of addresses.
This register is interpreted as a byte address. The lower three bits of this register are
always interpreted as 0, regardless of the value written. When reading the contents of
this register, the lower three bits will be read back as 0. This implies that the source
base address must be aligned to a 64-bit boundary.
Under many circumstances, this register will be initialized to the proper offset and
then changed only for special effects.
Acces
s
R/W
R/W
R/W
Acces
s
R/W
R/W
R/W
R/W
Value
-
-
-
Value
-
-
-
-
Rev. 3 — 17 March 2006
Description
Specifies the offset for pixel (0,0) of a source bitmap for XY to Linear
conversion of addresses. Bits 2:0 must be set to 0.
Description
Specifies endian-swapping on reads from memory.
When Swap[2] is 0, swapping is determined by the global endian
setting, possibly modified by BSI[0] in EngineConfig.
When Swap[2] is 1, swapping is determined by Swap[1:0] as shown:
00=No swapping. Memory is little-endian.
01=Bytes are swapped within each 16-bit word.
10=Words are swapped within each 32-bit double word.
11=Bytes are swapped within each 32-bit double word.
Specify the offset for pixel (0,0) of a destination bitmap for XY to
Linear conversion of addresses. Bits 2:0 must be set to 0.
Chapter 20: 2D Drawing Engine
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
20-16
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