PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 732
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 13: Receive filter block diagram
AcceptMulticastHashEn
AcceptUnicastHashEn
RxFilterEnWoL
AcceptBroadcastEn
AcceptMulticastEn
AcceptUnicastEn
RxFilterWoL
HashFilter
AND
CRC
OK?
Figure 13
On the top of the diagram, the Ethernet receive packet enters the filters. Each filter is
controlled by signals from the software view. Each filter produces a “Ready” output
and a “Match” output. If Ready is 0, then the Match value is “don’t care”; a filter will
assert its Ready output when it is finished. If the filter finds a packet that matches, it
will assert its Match output along with its Ready output. The results of the filters are
combined by logic functions into a single RxAbort output. If the RxAbort output is
asserted, the packet need not be received.
The blocks in the left-hand side of the diagram are used for WoL and are discussed in
Section
In order to reduce memory traffic, the Receive Datapath of the LAN100 has a FIFO
buffer that stores 68 bytes of receive data, so the LAN100 will only start writing the
received packet to memory after a 68-byte delay. If the RxAbort signal is asserted
during the initial 68 bytes of the packet, the packet can be discarded. The packet will
be removed from the buffer and not stored to memory at all, thereby also not using
any receive descriptors. If the RxAbort signal is asserted after the initial 68 bytes in a
packet, part of the packet is already written to memory, and the LAN100 will stop
writing further data in the packet to memory; the FailFilter bit in the status word of the
packet will be set to indicate the software device driver can discard the packet
immediately.
FReady
FMatch
Imperfect
AND
Hash
Filter
5.13.
depicts a functional view of the receive filter.
AND
AcceptPerfectEn
StationAddress
AndOr
Rev. 3 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
OR
Packet
AND
Perfect
Hash
Filter
AND/
OR
PatternMatchMask0/1/2/3
PatternMatchCRC0/1/2/3
PatternMatchSkip0/1/2/3
FMatch
FReady
PatternMatchJoin
PatternMatchEn
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
~FMatch
FReady
AND
RxAbort
Pattern
Match
Filter
23-63
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