PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 95
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
7.3 Memory Based Scaler
VIP shares its allocated pins with the FGPI module through an input router.
shows the different operating modes of VIP and FGPI modules.
The PNX15xx Series contains a Memory Based Scaler that performs operations on
images in main memory. The scaler hardware can either be controlled task by task by
the TM3260, or it can be given a list of scaling tasks. The performance of the scaler
on large images is typically limited either by the 120 Mpixel/s internal processing rate
or by the allocated main memory bandwidth.
The PNX15xx Series MBS can perform:
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Stores video data inside the video acquisition window in system memory in any
of the native pixel formats indicated in
rounding to convert the10-bit input to the selected format.
Provides an internal Test Pattern Generator with NTSC, PAL, and variable format
support.
Acquires VBI data using a separate acquisition window from the video acquisition
window.
Performs horizontal scaling, cropping and pixel packing on video data from a
continuous video data stream or from a single field or frame.
ANC header decoding or window mode for VBI data extraction.
Horizontal up scaling up to 2x.
Interrupt generation for VBI or video written to memory.
SD pixel frequency up to 81 MHz input clock (SD using up to 10-bit YUV CCIR-
656).
HD pixel frequency up to 81 MHz input clock (HD using 20-bit YUV input format).
color space conversion (mutually exclusive with scaling).
raw data capture up to 81 MHz in either 8- or 10-bit, packed mode with double
buffering.
de-interlacing using either a median, 2-field majority select, or 3-field majority
select algorithm with an edge detect/correct post-pass (these three provide
increasing quality, at the expense of increased bandwidth requirements)
edge detect/correct on an input frame that has been software de-interlaced (this
provides future capabilities in case we develop a better core de-interlacer than 3-
field majority select)
horizontal & vertical scaling (on the input image, or on the result of edge detect/
correct stage)
linear and non-linear aspect ratio conversion
anti flicker filtering
Rev. 3 — 17 March 2006
Table
5, and performs error feedback
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 2: Overview
Section 9.
2-14
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