CY7C63723-SC Cypress Semiconductor Corp, CY7C63723-SC Datasheet
CY7C63723-SC
Specifications of CY7C63723-SC
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CY7C63723-SC Summary of contents
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... Internal brown-out reset for suspend mode • Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.5VDC • Operating temperature from 0°C to 70°C • CY7C63723 available in 18-pin SOIC, 18-pin PDIP • CY7C63743 available in 24-pin SOIC, 24-pin PDIP, 24-pin QSOP • CY7C63722 available in DIE form • ...
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... The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an CY7C63722 CY7C63723 CY7C63743 12-bit Capture SPI ...
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... Programming voltage supply, ground for normal operation 14 15 Voltage supply 11 12 Voltage supply for 1.3-kΩ USB pull-up resistor (3.3V nominal). Also serves as P2.0 input Ground CY7C63722 CY7C63723 CY7C63743 CY7C63722-XC DIE P0 P0.7 P1 P1.1 P1 P1.3 P1.4 ...
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... The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above. CY7C63722 CY7C63723 CY7C63743 Page ...
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... PUSH X 7 SWAP A,X 4 SWAP A,DSP 6 MOV [expr],A 7 MOV [X+expr], [expr], [X+expr],A 7 AND [expr],A 5 AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] CY7C63722 CY7C63723 CY7C63743 Operand Opcode Cycles 20 4 acc direct 23 7 index 24 8 acc ...
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... JZ addr A0-AF JNZ addr B0-BF Document #: 38-08022 Rev. *B Opcode Cycles MNEMONIC 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI JNC 5 (or 4) JACC 5 (or 4) INDEX CY7C63722 CY7C63723 CY7C63743 Operand Opcode Cycles addr C0-CF 5 (or 4) addr D0-DF 5 (or 4) addr E0-EF 7 addr F0-FF 14 Page ...
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... USB endpoint 2 interrupt vector 0x000E SPI interrupt vector 0x0010 Capture timer A interrupt Vector 0x0012 Capture timer B interrupt vector 0x0014 GPIO interrupt vector 0x0016 Wake-up interrupt vector 0x0018 Program Memory begins here 0x1FDF 8 KB PROM ends here ( bytes). See Note below CY7C63722 CY7C63723 CY7C63743 Page ...
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... Interrupt enable for pins in Port 1 W Interrupt polarity for pins in Port 0 W Interrupt polarity for pins in Port 1 W Controls output configuration for Port Controls output configuration for Port 1 W CY7C63722 CY7C63723 CY7C63743 Function Fig. 12-2 12-3 12-8 21-4 21-5 21-6 21-7 12-4 ...
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... R Capture Timer status register R/W SPI read and write data register R/W SPI status and control register R/W Internal / External Clock configuration register R/W Processor status and control CY7C63722 CY7C63723 CY7C63743 Fig. 14-1 14-4 14-2 14-4 14-3 14-4 14-3 13-1 21-1 ...
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... When LVR the microcontroller enters a partial suspend state for a pe- riod of t START Program execution begins from address 0x0000 after this t delay period. This provides time for V START CY7C63722 CY7C63723 CY7C63743 XTALOUT XTALIN 2 1 Precision Internal External USB Clock Oscillator Clocking ...
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... The occurrence of a reset is recorded in the Processor Status and Control Register (Figure 20-1). Bits 4 (Low-voltage or Brown-out Reset bit) and 6 (Watchdog Reset bit) are used to record the occurrence of LVR/BOR and WDR respectively. The firmware can interrogate these bits to determine the cause of a reset. CY7C63722 CY7C63723 CY7C63743 Page ...
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... ROM . The LVR address 0x0000 MHz) 2–4 ms WDR goes HIGH for 2–4 ms CY7C63722 CY7C63723 CY7C63743 . Therefore, LVR should be enabled at all LVR . At that point, the t delay occurs before START delay. START (see Figure 10-1) of the last clear. Bit 6 ...
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... This can be done by timing the wake-up interrupt time with the accurate 1.024-ms timer interrupt, and adjusting the Timer Adjust bits accordingly to approximate the desired wake-up time. CY7C63722 CY7C63723 CY7C63743 Page ...
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... Figure 12-1. Block Diagram of GPIO Port (one pin shown) Port 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0 in the CY7C63723, or all 8 bits, P1.7–P1.0 in the CY7C63743 parts. Each bit can also be selected as an interrupt source for the microcontroller, as explained in Section 21.0. ...
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... Input thresholds are CMOS, or TTL as shown in the table (See Section 25.0 for the input threshold voltage in TTL or CMOS modes). Both input modes include hysteresis to minimize noise sensitivity. In suspend mode pin is used for a wake-up interrupt using an external R-C circuit, CMOS mode is preferred for lowest power. CY7C63722 CY7C63723 CY7C63743 P1[7:0] Mode1 ...
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... The host generates control reads from the device to request the Configuration and Report descriptors. 10.Once the device receives a Set Configuration request, its functions may now be used. 11.Firmware should take appropriate action for Endpoint 1 and/or 2 transactions, which may occur from this point. CY7C63722 CY7C63723 CY7C63743 Page ...
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... CY7C63722 CY7C63723 CY7C63743 Control Action Application Not forcing (SIE controls driver) Any Mode Force K (D+ HIGH, D– LOW) USB Mode Force J (D+ LOW, D– HIGH) Force SE0 (D– LOW, D+ LOW) Force D– LOW, D+ LOW PS/2 Mode Force D– ...
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... The mode encoding is shown in Table 22-1. Additional information on the mode bits can found in Table 22-2 and Table 22-3. These modes give the firmware total control on how to respond to different tokens sent to the endpoints from the host. CY7C63722 CY7C63723 CY7C63743 Page ...
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... For Endpoint 0 Count Register, whenever the count up- dates from a SETUP or OUT transaction, the count register locks and cannot be written by the CPU. Reading the reg- ister unlocks it. This prevents firmware from overwriting a status update on incoming SETUP or OUT transactions be- fore firmware has a chance to read the data. CY7C63722 CY7C63723 CY7C63743 ...
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... The PS/2 on-chip support circuitry is illustrated in Figure 16-1. 200Ω 3.3V Regulator V CC PS/2 Pull-up Enable 5 kΩ 5 kΩ USB - PS/2 Driver Port 2.4 On-chip CY7C63722 CY7C63723 CY7C63743 pin can be placed into a high-impedance state, VREG 1.3 kΩ D+/SCLK D–/SDATA Off-chip Page ...
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... Section 12.0 for GPIO configuration details. 17.2 Master SCK Selection The Master’s SCK is programmable to one of four clock settings, as shown in Figure 17-1. The frequency is selected with the Clock Select Bits of the SPI control register. The CY7C63722 CY7C63723 CY7C63743 MOSI Master / Slave MISO Control ...
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... SPI Clock Polarity bit SCK idles HIGH SCK idles LOW. Bit 2: CPHA SPI Clock Phase bit (see Figure 17-4) Bit [1:0]: SCK Select Master mode SCK frequency selection (no effect in Slave Mode Mbit Mbit 0.5 Mbit 0.0625 Mbit/s CY7C63722 CY7C63723 CY7C63743 SCK Select R/W R/W R ...
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... For Master Mode, Firmware sets SS, may use any GPIO pin. For Slave Mode active LOW input. P0.5 Data output for master, data input for slave. P0.6 Data input for master, data output for slave. P0.7 SPI Clock: Output for master, input for slave. CY7C63722 CY7C63723 CY7C63743 LSB x LSB Comment Page ...
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... Bit # Bit Name Read/Write Reset Figure 18-2. Timer MSB Register (Address 0x25) Bit [7:4]: Reserved Bit [3:0]: Timer upper four bits Figure 18-3. Timer Block Diagram CY7C63722 CY7C63723 CY7C63743 Reserved Timer [11: 1.024-ms interrupt µ 128- s interrupt 0 1 MHz clock Timer Registers ...
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... Timer A Falling Edge Time Timer B Rising Edge Time Timer B Falling Edge Time Figure 19-1. Capture Timers Block Diagram Bit # Bit Name Read/Write Reset Figure 19-2. Capture Timer A-Rising, Data Register CY7C63722 CY7C63723 CY7C63743 1 MHz Clock Capture Timer A Interrupt Request Capture Timer B Interrupt Request 7 ...
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... Table 19-1. Capture Timer Prescalar Settings (Step size and range for F Prescale 2:0 000 Bits 7:0 of free-running timer 001 Bits 8:1 of free-running timer 010 Bits 9:2 of free-running timer 011 Bits 10:3 of free-running timer 100 Bits 11:4 of free-running timer CY7C63722 CY7C63723 CY7C63743 Prescale Bit Capture Capture Capture [2: ...
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... Status and Control Register after power-up. Normally the LVR/BOR bit should be cleared so that a subsequent WDR can be clearly identified. Note that if a USB bus reset (long SE0) is received before firmware examines this register, the Bus Interrupt Event bit would also be set. CY7C63722 CY7C63723 CY7C63743 Interrupt ...
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... Interrupt Service Routine will execute a minimum of 16 clocks (1+10+ maximum of 20 clocks (5+10+5) after the interrupt is issued. With a 6-MHz external resonator, internal CPU clock speed is 12 MHz clocks take 20/12 MHz = 1.67 µs. CY7C63722 CY7C63723 CY7C63743 Function Page ...
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... USB bus reset condition, or PS/2 activity. The selection is made with the USB-PS/2 Interrupt Mode bit in the USB Status and Control Register (Figure 13-1). In either case, the interrupt will occur if the selected condition exists for 256 µs, and may occur as early as 128 µs. CY7C63722 CY7C63723 CY7C63743 1.024-ms 128-µ ...
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... USB host during the host attempts to read data from the endpoint (INs). • The device SIE sends a NAK or STALL handshake pack the USB host during the host attempts to write data (OUTs) to the endpoint FIFO Enable EP0 interrupt 0 = Disable EP0 interrupt CY7C63722 CY7C63723 CY7C63743 Page ...
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... Rising GPIO edge Falling GPIO edge Bit # Bit Name Read/Write Reset Figure 21-7. Port 1 Interrupt Polarity Register CY7C63722 CY7C63723 CY7C63743 To CPU CPU IRQ Pending (Bit 7, Reg 0xFF) IRQ Global Int Enable Interrupt Sense Enable (Bit 2, Reg 0xFF) Bit Controlled by DI, EI, and CLR ...
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... This mode is changed by the SIE to mode 1100 on STALL Ignore issuance of ACK handshake NAK Check An ACK from mode 1111 changes the mode to 1110 TX Count Check This mode is changed by the SIE to mode 1110 on issuance of ACK handshake CY7C63722 CY7C63723 CY7C63743 IRQout Interrupt Priority Interrupt Encoder Vector Page ...
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... Setup In Bit[3:0], Figure 14-4 Data Valid (Bit 6, Figure 14-4) Data 0/1 (Bit 7, Figure 14-4) PID Status Bits (Bit[7:5], Figure 14-2) TX: transmit TX0: transmit 0-length packet RX: receive CY7C63722 CY7C63723 CY7C63743 Interrupt? End Point Mode Out ACK Response Int SIE’s Response Endpoint Mode changed by the SIE ...
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... UC x updates updates updates UC invalid updates 0 updates valid invalid valid invalid CY7C63722 CY7C63723 CY7C63743 Set End Point Mode IN OUT ACK Response ACK NoChange Ignore NoChange Ignore NoChange Ignore NoChange NAK NoChange Ignore NoChange Ignore NoChange NAK NoChange Ignore NoChange Ignore ...
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... valid invalid valid invalid updates updates updates updates CY7C63722 CY7C63723 CY7C63743 NoChange ACK STALL STALL NoChange Ignore NoChange Ignore ACK (back NoChange ACK STALL IN OUT ACK response STALL NoChange Ignore NoChange Ignore NoChange NAK NoChange ACK STALL STALL ...
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... FOR FOR Table 22-3. Details of Modes for Differing Traffic Conditions (continued OUT Reserved Out Document #: 38-08022 Rev CY7C63722 CY7C63723 CY7C63743 NoChange Ignore NoChange NAK NoChange Ignore NoChange TX Page yes no yes ...
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... Falling Intr Rising Intr Enable Reserved Capture B Capture B Falling Rising Event Event Watch Dog Bus LVR/BOR Suspend Reset Interrupt Reset Event CY7C63722 CY7C63723 CY7C63743 Read/Write/ Bit 2 Bit 1 Bit 0 Both/ 00000000 BBBBBBBB 00000000 BBBBBBBB P2.1 (Int Clk VREG Pin -- -- 00000000 RR RR Mode Only ...
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... Cumulative across all ports V below V for >100 ns CC LVR [8] linear ramp [9, 10] Load = External cap not required [ Gnd suspend or with LVR disabled, BOR occurs whenever V LVR is connected from D– to ground. PD CY7C63722 CY7C63723 CY7C63743 +0.5V CC +0.5V CC Min. Max. Unit V 5.5 V LVR 4.35 5. µA 25 µA 75 – ...
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... High to low edge, Port High to low edge, Port Ports 0, 1, and 2 [ mA, Ports OL1 [ mA, Ports OL1 [ mA, Ports OL2 [ mA, Ports OL3 [4] Port Internal Clock Mode only CY7C63722 CY7C63723 CY7C63743 Min. Max. Unit 0.3 V 2.7 3.6 V 0.2 V 0.8 2.5 V 0.8 2 µA –10 10 1.274 1.326 kΩ ...
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... For Paired Transitions [15] Accepts as EOP To next transition, Figure 26-5 To paired transition, Figure 26-5 Note 16 CLoad = 150 pF to 600 pF [17] See Figures 26-6 to 26-9 F /3; see Figure 17-1 CLK CY7C63722 CY7C63723 CY7C63743 Min. Max. Unit 5.7 6.3 MHz 5.91 6.09 MHz 164.2 169 ...
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... Time before leading SCK edge SCK to data valid Time after SS LOW to data valid Before first SCK edge After last SCK edge T CYC Figure 26-1. Clock Timing 90% 90% 10% 10% Figure 26-2. USB Data Signal Timing CY7C63722 CY7C63723 CY7C63743 Min. Max. Unit 125 ns 125 ns – 100 ...
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... Figure 26-3. Receiver Jitter Tolerance Crossover Point Extended Point Diff. Data to SE0 Skew + T PERIOD DEOP Crossover Points Consecutive Transitions PERIOD xJR1 Paired Transitions PERIOD xJR2 Figure 26-5. Differential Data Jitter CY7C63722 CY7C63723 CY7C63743 T JR1 JR2 Source EOP Width: T EOPT Receiver EOP Width EOPR1 EOPR2 Page ...
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... SSU SDO MISO Document #: 38-08022 Rev. *B (SS is under firmware control in SPI Master mode) T SCKL MSB T MHD Figure 26-6. SPI Master Timing, CPHA = 0 T SCKL T SHD MSB Figure 26-7. SPI Slave Timing, CPHA = 0 CY7C63722 CY7C63723 CY7C63743 LSB LSB T SSH LSB LSB Page ...
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... SSU SHD T SDO1 MISO MSB Document #: 38-08022 Rev. *B (SS is under firmware control in SPI Master mode) T SCKL T MDO Figure 26-8. SPI Master Timing, CPHA = 1 T SCKL T SDO Figure 26-9. SPI Slave Timing, CPHA = 1 CY7C63722 CY7C63723 CY7C63743 LSB LSB T SSH LSB LSB Page ...
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... FOR FOR 27.0 Ordering Information Ordering Code EPROM Size CY7C63723- CY7C63723-PXC 8 KB CY7C63723- CY7C63723-SXC 8 KB CY7C63743-QXC 8 KB CY7C63743- CY7C63743-PXC 8 KB CY7C63743- CY7C63743-SXC 8 KB CY7C63722- CY7C63722-XWC 8 KB 28.0 Package Diagrams Document #: 38-08022 Rev. *B Package Package Type Name P3 18-Pin (300-Mil) PDIP P3 18-Pin (300-Mil) Lead-free PDIP ...
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... REFERENCE JEDEC MO-119 0.419[10.642] 0.291[7.391] 0.300[7.620] PACKAGE WEIGHT 0.65gms 24 0.026[0.660] 0.032[0.812] SEATING PLANE 0.092[2.336] 0.105[2.667] 0.004[0.101] * 0.004[0.101] 0.0118[0.299] CY7C63722 CY7C63723 CY7C63743 MIN. MAX. PART # S18.3 STANDARD PKG. SZ18.3 LEAD FREE PKG. * 51-85023-A 0.0091[0.231] 0.015[0.381] 0.0125[0.317] 0.050[1.270] 51-85023-*B MIN. MAX. PART # S24 ...
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... FOR FOR 28.0 Package Diagrams (continued) Document #: 38-08022 Rev. *B 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) PDIP P13 CY7C63722 CY7C63723 CY7C63743 51-85055-*B 51-85013-*B Page ...
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... D– 1662.35 D+ 1735.35 P1.7 1752.05 P1.5 1752.05 P1.3 1752.05 P1.1 1752.05 P0.7 1752.05 P0.6 1393.25 P0.5 1171.80 P0.4 980.35 CY7C63722 CY7C63723 CY7C63743 Y (microns) 2843.15 2843.15 2843.15 2687.95 2496.45 2305.05 2113.60 1922.05 1730.90 312.50 184.85 184.85 184.85 184.85 184.85 184.85 289.85 1832.75 2024 ...
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... FOR FOR Document History Page Document Title: CY7C63722, CY7C63723, CY7C63743 enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller Document Number: 38-08022 Orig. of REV. ECN NO. Issue Date Change ** 118643 10/22/02 *A 243308 SEE ECN *B 267229 See ECN Document #: 38-08022 Rev. *B Description of Change BON Converted from Spec 38-00944 to Spec 38-08022 ...