ADE7569ASTZF16 Analog Devices Inc, ADE7569ASTZF16 Datasheet
ADE7569ASTZF16
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ADE7569ASTZF16 Summary of contents
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 GENERAL FEATURES Wide supply voltage operation: 2 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power saving modes (PSM) Full operation 1.6 mA (PLL clock dependent) Battery mode: ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TABLE OF CONTENTS General Features ............................................................................... 1 Energy Measurement Features ........................................................ 1 Microprocessor Features .................................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Functional Block Diagrams ............................................................. 4 Specifications ..................................................................................... 6 Energy Metering ........................................................................... 6 Analog Peripherals ....................................................................... ...
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LCD Driver ................................................................................... 100 LCD Registers ........................................................................... 100 LCD Setup ................................................................................. 103 LCD Timing and Waveforms ................................................. 103 Blink Mode ................................................................................ 104 Display Element Control ......................................................... 104 Voltage Generation .................................................................. 105 LCD External Circuitry ........................................................... 106 LCD Function in PSM2 ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 GENERAL DESCRIPTION The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ 1 ADE7569 integrate the Analog Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, an RTC, an LCD driver, and all the peripherals to ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 1.20V REF SPI/I SERIAL INTERFACE + PGA1 ADC – ENERGY – MEASUREMENT PGA1 ADC I + DSP PGA2 ADC V ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SPECIFICATIONS V = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz ENERGY METERING Table 2. Parameter 1 MEASUREMENT ACCURACY Phase Error Between Channels 0.8 Capacitive PF ...
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ANALOG PERIPHERALS Table 3. Parameter INTERNAL ADCs (BATTERY, TEMPERATURE, V Power Supply Operating Range 2 No Missing Codes Conversion Delay 3 ADC Gain V Measurement DCIN V Measurement BAT Temperature Measurement ADC Offset V Measurement DCIN V ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Parameter LCD, RESISTOR LADDER ACTIVE Leakage Current V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage ON-CHIP REFERENCE Reference Error Power Supply Rejection Temperature Coefficient 2 1 This function is not available in the ADE7116. 2 ...
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Parameter POWER SUPPLY INPUTS BAT INTERNAL POWER SUPPLY SWITCH (V SWOUT Resistance BAT SWOUT Resistance DD SWOUT V to/from V Switching Open Time BAT DD BCTRL State Change and ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TIMING SPECIFICATIONS AC inputs during testing were driven at V and at 0.45 V for Logic 0. Timing measurements were made at V minimum for Logic 1 and at V maximum for Logic 0, as shown in IL Figure ...
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Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge ...
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Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 11. Parameter V to DGND DGND BAT V to DGND DCIN Input LCD Voltage to AGND, LCDVA, 1 LCDVB, LCDVC Analog Input Voltage to AGND, V ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS COM3/FP27 COM2/FP28 P1.2/FP25 P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 NOTES RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP BE CONNECTED TO THE GROUND ...
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Pin No. Mnemonic Description 18 LCDVA This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, it ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Pin No. Mnemonic Description 60 V 3.3 V Power Supply Input from the Regulator. This pin is connected internally selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF ...
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COM3/FP27 COM2/FP28 P1.2/FP25 P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 NOTES RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP BE CONNECTED TO THE GROUND PLANE ON THE BOARD. Figure 10. ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Pin No. Mnemonic Description 18 LCDVA In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this ...
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Pin No. Mnemonic Description 59 V This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to INTA this pin. This pin should be decoupled with a 10 μF capacitor in parallel ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 MID CLASS C GAIN = 1 INTEGRATOR OFF 1.5 INTERNAL REFERENCE 1.0 0.5 +25° +85° –40° –0.5 –1.0 –1.5 MID CLASS C –2.0 0.1 1 ...
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GAIN = 1 INTEGRATOR OFF 0.4 INTERNAL REFERENCE 0.3 0 3.3V rms I ; 3.3V rms 0 3.43V rms 0 –0 3.13V rms –0.2 –0.3 –0.4 –0.5 0.1 1 CURRENT CHANNEL (% of ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 2.0 MID CLASS C GAIN = 16 INTEGRATOR OFF 1.5 INTERNAL REFERENCE 1.0 0.5 +25° –40° –0.5 +85° –1.0 –1.5 MID CLASS C –2.0 0.1 1 CURRENT CHANNEL (% ...
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PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY 2.0 GAIN = 16 MID CLASS C INTEGRATOR ON 1.5 INTERNAL REFERENCE 1.0 –40° +85° 0.5 +25° 0.5 0.5 –40° 0.5 0 +25°C; ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is defined by the following formula: Percentage Error = ⎛ ⎞ − Energy Register True Energy ⎜ ⎜ × ⎟ ⎟ ⎝ ⎠ True Energy ...
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SPECIAL FUNCTION REGISTER (SFR) MAPPING Table 15. Mnemonic Address Description INTPR 0xFF Interrupt pins configuration (see Table 17). SCRATCH4 0xFE Scratch Pad 4 (see Table 25). SCRATCH3 0xFD Scratch Pad 3 (see Table 24). SCRATCH2 0xFC Scratch Pad 2 (see ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Mnemonic Address Description HTHSEC 0xA2 RTC hundredths of a second counter (see Table 129). TIMECON 0xA1 RTC configuration (see Table 128). P2 0xA0 Port 2 (see Table 162). EPCFG 0x9F Extended port configuration (see Table 156). SBAUDT 0x9E Enhanced ...
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POWER MANAGEMENT The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have elaborate power management circuitry that manages the switchover from regular power supply to battery Table 16. Power Management SFRs SFR Address R/W Mnemonic 0xEC R/W IPSME 0xF5 R/W BATPR 0xF8 R/W IPSMF 0xFF R/W ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8) Bit Bit Address Mnemonic Default 7 0xFF FPSR 0 6 0xFE FPSM 0 5 0xFD FSAG 0 4 0xFC Reserved 0xFB FVADC 0xFA ...
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Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB) Bit Mnemonic Default Description [7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 23. Scratch Pad 2 SFR (SCRATCH2, ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 POWER SUPPLY ARCHITECTURE Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has two power supply inputs, V require only a single 3.3 V power supply battery backup, or secondary power supply, with a maximum of 3.7 V can be connected to ...
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POWER SUPPLY MANAGEMENT (PSM) INTERRUPT The power supply monitor interrupt alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the interrupt enable and Priority 2 SFR (IEIP2, Address 0xA9) ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Battery Switchover and Power Supply Restored PSM Interrupt The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can be configured to generate a PSM interrupt when the source of V changes from V SWOUT DD battery switchover. Setting the EBSO bit in the power manage- ...
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USING THE POWER SUPPLY FEATURES In an energy meter application, the 3.3 V power supply (V typically generated from the ac line voltage and regulated to 3 voltage regulator IC. The preregulated dc voltage, typically 5 V ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 27. Power Supply Event Timing Operating Modes Parameter Time Description min Time between when min Time between when typ Time between when V 3 battery ...
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OPERATING MODES PSM0 (NORMAL MODE) In PSM0, or normal operating mode All of the analog circuitry and the digital circuitry powered and V are enabled by default. In normal mode, the INTD INTA default ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 3.3 V PERIPHERALS AND WAKE-UP EVENTS Some of the 3.3 V peripherals are capable of waking the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2 mode. The events that can cause the devices to wake up from PSM2 mode are listed in the ...
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TRANSITIONING BETWEEN OPERATING MODES The operating mode of the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 is determined by the power supply connected Therefore, changes in the power SWOUT supply, such as when V switches from V SWOUT V switches to V ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ENERGY MEASUREMENT The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access ...
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Table 31. Energy Measurement SFRs Address R/W Mnemonic 0x91 R/W MADDPT 0x92 R/W MDATL 0x93 R/W MDATM 0x94 R/W MDATH 0xD1 R VRMSL 0xD2 R VRMSM 0xD3 R VRMSH 0xD4 R IRMSL 0xD5 R IRMSM 0xD6 R IRMSH 0xD9 R/W ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ×1, ×2, ×4, ×8, ×16 {GAIN[2:0 PGA1 I ADC HPF I N PGA1 ADC HPF I PB IBGAIN[11: PGA2 ADC V 2N Figure 40. ADE7116, ADE7156, ADE7166, and ADE7169 Energy Metering Block Diagram INTEGRATOR WGAIN[11:0] ...
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ENERGY MEASUREMENT REGISTERS Table 32. Energy Measurement Register List Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x01 WATTHR R 24 0x02 RWATTHR R 24 0x03 LWATTHR R 24 0x04 VARHR 0x05 RVARHR 0x06 LVARHR ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x25 VARDIV R/W 8 0x26 VADIV R/W 8 0x27 CF1NUM R/W 16 0x28 CF1DEN R/W 16 0x29 CF2NUM R/W 16 0x2A CF2DEN R/W 16 0x3B Reserved 0x3C Reserved 2 0x3D CALMODE R/W 8 ...
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Bit Mnemonic Default 1 FREQSEL 0 0 WAVEN 0 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 35. Waveform Mode Register (WAVMODE, Address 0x0D) Bit Mnemonic Default [7:5] WAV2SEL 000 [4:2] WAV1SEL 000 [1: ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Bit Mnemonic Default 1 [3:2] VARNOLOAD 00 [1:0] APNOLOAD 00 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F) Bit Mnemonic Default 7 ICHANNEL ...
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Bit Mnemonic Default 3 CFSIGN_OPT 0 [2:0] PGA1 000 1 This gain is not recommended in the ADE7166 or ADE7169 because it can create an overranging of the ADC when both current inputs are in opposite phase. Table 39. Calibration ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD) Bit Interrupt Flag Description 7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not enabled ...
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Table 45. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) Bit Interrupt Enable Bit Description [7:6] Reserved Reserved. 5 WFSM When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core. ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ANALOG-TO-DIGITAL CONVERSION Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has two Σ-Δ analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In ...
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Antialiasing Filter Figure 44 also shows an analog LPF (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency com- ponents in the input signal to ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ×1, ×2, ×4 ×8, ×16 REFERENCE {GAIN[2:0 PGA1 ADC 0.25V, 0.125V, 62.5mV, 31.3mV 0V ANALOG INPUT RANGE *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE ...
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Voltage Channel ADC Figure 48 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 FAULT DETECTION The ADE7116/ADE7156/ADE7166/ADE7169 incorporate a fault detection scheme that warns of fault conditions and allows the part to continue accurate measurement during a fault event. (This function is not available in the ADE7566/ ADE7569.) The ADE7116/ADE7156/ADE7166/ADE7169 do this ...
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Fault with Inactive Input Greater Than Active Input If the difference between I , the inactive input, and I PB active input (that is, being used for billing), becomes greater than 6.25 and the FAULTSIGN bit (Bit ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The ADE7169/ADE7569 have a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on the current channel is switched off by default when the ADE7169/ADE7569 are powered up. Setting the INTE bit (Bit ...
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POWER QUALITY MEASUREMENTS Zero-Crossing Detection Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce a zero-crossing internal signal (ZX) and is used in calibration mode. The zero crossing is generated ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Line Voltage SAG Detection In addition to detection of the loss of the line voltage signal (zero crossing), the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 can also be programmed to detect when the absolute value of the line voltage drops below a certain ...
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PHASE COMPENSATION The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The update rate of the current channel rms measurement is 4.096 MHz/5. To minimize noise in the reading of the register, the I register can also be configured to update only with the rms zero crossing of the voltage ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 MODE1[5] HPF I DIGITAL PA INTEGRATOR* dt HPF I PB IBGAIN *NOT AVAILABLE IN THE ADE7116, ADE7156, OR ADE7166. Figure 62. ADE7116/ADE7156/ADE7166/ADE7169 Current Channel RMS Signal Processing with PGA1 = VOLTAGE SIGNAL (V(t)) 0x28F5 ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Voltage Channel RMS Calculation Figure 63 shows details of the signal processing chain for the rms calculation on the voltage channel. This voltage rms estimation is done in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 using the mean absolute value calculation, as shown ...
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FREQUENCY (Hz) Figure 65. Frequency Response of LPF2 Active Power Gain Calibration Figure 66 shows the signal processing chain for the active power calculation in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569. The active ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ACTIVE ENERGY CALCULATION As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed mathematically, as shown in Equation 13 where power. ...
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Figure 67 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ACTIVE ENERGY NO-LOAD THRESHOLD ACTIVE POWER NO-LOAD THRESHOLD APSIGN FLAG APNOLOAD POS INTERRUPT STATUS REGISTERS Figure 69. Energy Accumulation in Absolute Accumulation Mode Active Energy Pulse Output All of the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 circuitry has a pulse output whose frequency ...
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When a new half-line cycle is written in the LINCYC register (Address 0x12), the LWATTHR register (Address 0x03) is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Reactive Power Gain Calibration Figure 72 shows the signal processing chain for the ADE7169/ ADE7569 reactive power calculation. As explained in the Reactive Power Calculation (ADE7169/ADE7569) section, the reactive power is calculated by applying a low-pass filter to the ...
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The reactive energy accumulation depends on the setting of the SAVARM and ABSVARM bits in the ACCMODE register (Address 0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the reactive energy contents. ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Integration Time Under Steady Load: Reactive Energy As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the ...
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Var Absolute Accumulation Mode The ADE7169/ADE7569 are placed in absolute accumulation mode by setting the ABSVARM bit (Bit 3) in the ACCMODE register (Address 0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. V and I are the effective voltage and rms rms current delivered to the load, respectively. Therefore, the apparent power (AP) ...
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APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power. = ∫ Apparent Energy Apparent Power The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 achieve the integration of the apparent power signal by continuously accumulating the apparent power signal in ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Apparent Energy Pulse Output All the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also ...
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APPARENT POWER LPF1 FROM VOLTAGE CHANNEL ADC ENERGY-TO-FREQUENCY CONVERSION The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 also provide two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verifies the energy meter calibration. One convenient way to ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 written to any of these registers applied to the register. The ratio of CFxNUM/CFxDEN should be less than 1 to ensure proper operation. If the ratio of the CFxNUM/CFxDEN registers is greater than 1, ...
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TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 include temperature measurements as well as battery and supply voltage measurements. (This feature is not available in the ADE7116.) These measurements enable many forms of compensation. The temperature and supply voltage measurements ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 50. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3) Bit Mnemonic Default [7:6] Reserved 0 [5:3] TEMP_DIFF 0 [2:0] VDCIN_DIFF 0 Table 51. Start ADC Measurement SFR (ADCGO, Address 0xD8) Bit Address Mnemonic 7 0xDF PLLACK [6:3] 0xDE ...
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TEMPERATURE MEASUREMENT To provide a digital temperature measurement, each ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated ADC. An 8-bit temperature ADC value SFR (TEMPADC, Address 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. There ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit (Bit 2) in the power management interrupt enable SFR (IPSME, Address 0xEC). This method allows battery measurements to take place completely in ...
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External Voltage ADC in PSM0, PSM1, and PSM2 Modes An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569. • In PSM0 operating mode, the 8052 is active. External voltage ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 8052 MCU CORE ARCHITECTURE The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have an 8052 MCU core and use the 8052 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and ...
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Table 58. Program Control SFR (PCON, Address 0x87) Bit Mnemonic Default 7 SMOD 0 [6:0] Reserved 0 Table 59. Data Pointer Low SFR (DPL, Address 0x82) Bit Mnemonic Default [7:0] DPL 0 Table 60. Data Pointer High SFR (DPH, Address ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 BASIC 8052 REGISTERS Program Counter (PC) The program counter holds the 2-byte address of the next instruction to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that the ...
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STANDARD 8052 SFRs The standard 8052 SFRs include the accumulator (ACC), B, PSW, DPTR, and SP SFRs, as described in the Basic 8052 Registers section. The 8052 also defines standard timers, serial port interfaces, interrupts, I/O ports, and power-down modes. ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Address 0x80 through Address 0xFF of general-purpose RAM are shared with the SFRs. The mode of addressing determines which memory space is accessed, as shown in Figure 84. 0xFF ACCESSIBLE BY ACCESSIBLE BY INDIRECT ADDRESSING DIRECT ADDRESSING ONLY 0x80 ...
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Immediate Addressing In immediate addressing, the expression entered after the number sign (#) is evaluated by the assembler and stored in the memory address specified. This number is referred literal because it refers only to a value ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 INSTRUCTION SET Table 65 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4-MIPS peak performance. Note that throughout this section, A represents the accumulator. ...
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Mnemonic Description RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry Data Transfer MOV A,Rn Move register to A MOV A,@Ri Move indirect memory to A MOV Rn,A Move A ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Mnemonic Description JNC rel Jump on carry equal rel Jump on accumulator = 0 JNZ rel Jump on accumulator ≠ 0 DJNZ Rn,rel Decrement register, JNZ relative LJMP Long jump unconditional LCALL addr16 Long jump to ...
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SUBB A, Source This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag. Table 69. SUBB A (Source) Affected Status Flags Flag Description C Set if there is a ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 DUAL DATA POINTERS Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON, Address 0xA7). DPCON features automatic hardware postincrement and postdecrement, as ...
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INTERRUPT SYSTEM The unique power management architecture of the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. A ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 79. Interrupt Priority SFR (IP, Address 0xB8) Bit Bit Address Mnemonic 7 0xBF PADE 6 0xBE PTEMP 5 0xBD PT2 4 0xBC PS 3 0xBB PT1 2 0xBA PX1 1 0xB9 PT0 0 0xB8 PX0 Table 80. Interrupt ...
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INTERRUPT FLAGS The interrupt flags and status flags associated with the interrupt vectors are shown in Table 82 and Table 83. Most of the interrupts have flags associated with them. Table 82. Interrupt Flags Interrupt Source Flag IE0 TCON.1 TF0 ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 IPSMF FPSM PSM (IPSMF.6) IPSME MIDNIGHT RTC ALARM MIRQSTH MIRQSTM MIRQSTL ADE MIRQENH MIRQENM MIRQENL WATCHDOG TIMEOUT WATCHDOG WDIR TEMPADC INTERRUPT TEMP ADC* IT0 0 INT0 EXTERNAL INTERRUPT 0 1 TF0 TIMER 0 IT1 0 EXTERNAL INT1 INTERRUPT 1 ...
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INTERRUPT VECTORS When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by ...
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Table 86. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA) Bit Mnemonic Default 7 WDPROT_PROTKY7 1 [6:0] PROTKY[6:0] 0xFF Writing to the Watchdog Timer SFR (WDCON, Address 0xC0) Writing data to the WDCON SFR involves a double ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 functions capable of driving LCDs with 2×, 3×, and 4× multi- plexing. ...
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Table 89. LCD Configuration X SFR (LCDCONX, Address 0x9C) Bit Mnemonic Default 7 Reserved 0 6 EXTRES 0 [5:0] BIASLV 0 1 This feature is not available in the ADE7116. Table 90. LCD Bias Voltage When Contrast Control Is Enabled ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 93. LCD Frame Rate Selection for f FD3 FD2 FD1 FD0 f (Hz) LCD 256 170 128 102 ...
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Table 95. LCD Segment Enable SFR (LCDSEGE, Address 0x97) Bit Mnemonic Default 7 FP25EN 0 6 FP24EN 0 5 FP23EN 0 4 FP22EN 0 3 FP21EN 0 2 FP20EN 0 [1:0] Reserved 0 Table 96. LCD Pointer SFR (LCDPTR, Address ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The LCD waveform frequency the frequency at which LCD the LCD switches the active common line. Thus, the LCD waveform frequency depends heavily on the multiplex level. The frame rate and LCD waveform frequency are set ...
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Table 99. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR (LCDDAT Address 0xAE) LCD Pointer SFR (LCDPTR, Address 0xAC) LCD Memory Address COM3 0x0E 0x0D FP27 0x0C FP25 0x0B FP23 ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 LCD EXTERNAL CIRCUITRY The voltage generation selection is made by the EXTRES bit (Bit 6) in the LCD configuration X SFR (LCDCONX, Address 0x9C). This bit is cleared by default for charge pump voltage generation, but it can be ...
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The LCD is set up with the following 8052 code: ; set up LCD pins to have LCD functionality MOV LCDSEG,#FP20EN+FP21EN+FP22EN+FP23EN MOV LCDSEGX,#FP16EN+FP17EN+FP18EN+FP19EN ; set up LCDCON for f =2048Hz, 1/3 bias and 4x multiplexing LCDCLK MOV LCDCON,#BIAS+LMUX1+LMUX0 ; setup ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 FLASH MEMORY FLASH MEMORY OVERVIEW Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default, erased state of a byte of flash memory is 0xFF. When a byte of flash memory is programmed, the required ...
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FLASH MEMORY ORGANIZATION The 16 kB array of flash memory provided by the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 are segmented into 32 pages of 512 bytes each the user to decide which flash memory used for ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 EADRH PROTECTION KEY ECON—Flash Control SFR Programming flash memory is done through the Flash Control SFR (ECON, Address 0xB9). This SFR allows the user to read, write, erase, or verify the flash memory method ...
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Table 106. Flash Write/Erase Protection 0 SFR (PROTB0, Address 0xBD) Bit Mnemonic Default Description [7:0] PROTB0 0xFF This SFR is used to write the write/erase protection bits for Page 0 to Page 7 of the flash memory (see the Protecting ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Erase All Erase all of the 16 kB flash memory. MOV FLSHKY,#3Bh ; Write Flash security key. MOV ECON,#03h ; Erase all Read Byte Read flash memory byte 0x3C00. MOV EADRH,#3Ch ; Setup byte address MOV EADRL,#00h MOV FLSHKY,#3Bh ...
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PROTECTING THE FLASH MEMORY Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected cannot be read by the end user. The write protection ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Enabling Flash Protection by Emulator Commands Another way to set the flash protection bytes is to use the reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate ...
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TIMERS Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has three 16-bit timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/Counter 2. The timer/counter hardware is included on-chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88) Bit Bit Address Mnemonic Default 7 0x8F TF1 0 6 0x8E TR1 0 5 0x8D TF0 0 4 0x8C TR0 0x8B IE1 0 1 ...
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Table 116. Timer 0 High Byte SFR (TH0, Address 0x8C) Bit Mnemonic Default Description [7:0] TH0 0 Timer 0 data high byte. Table 117. Timer 0 Low Byte SFR (TL0, Address 0x8A) Bit Mnemonic Default Description [7:0] TL0 0 Timer ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 99. Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents ...
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In either case, if Timer 2 is used to generate the baud rate, the TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts do not occur and do not have to be disabled. In this mode, the EXF2 flag ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PLL The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this ...
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REAL-TIME CLOCK (RTC) The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have an embedded real-time clock (RTC) as shown in Figure 103. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 128. RTC Configuration SFR (TIMECON, Address 0xA1) Bit Mnemonic Default Description 7 MIDNIGHT 0 Midnight flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the ...
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Table 133. RTC Alarm Interval SFR (INTVAL, Address 0xA6) Bit Mnemonic Default Description [7:0] INTVAL 0 The interval timer counts according to the time base established in the ITS bits of the RTC configuration SFR (TIMECON, 0xA1). When the number ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 READ AND WRITE OPERATIONS Writing to the RTC Registers The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, the hundredths of a second counter SFR (HTHSEC, Address 0xA2), seconds counter SFR (SEC, Address 0xA3), minutes counter ...
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Take care when changing the interval timer time base. The recommended procedure is as follows the alarm interval SFR (INTVAL, Address 0xA6) is going to be modified, write to this register first. Then, wait for one 128 Hz ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 UART SERIAL INTERFACE The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 UART can be configured in one of four modes. • Shift register with baud rate fixed at f • 8-bit UART with variable baud rate • 9-bit UART with baud rate fixed at ...
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Table 141. Serial Port Buffer SFR (SBUF, Address 0x99) Bit Mnemonic [7:0] SBUF Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E) Bit Mnemonic Default 7 OWE [4:3] SBTH 0 [2:0] ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 144. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock Ideal Baud CD 115,200 0 115,200 1 57,600 0 57,600 1 38,400 0 38,400 1 38,400 2 19,200 0 19,200 1 19,200 2 19,200 3 ...
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UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at f Mode 0 is selected when the SM0 and SM1 bits in the serial communications control register SFR (SCON, Address 0x98) are cleared. In this shift register mode, ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 To transmit, the eight data bits must be written into the serial port buffer SFR (SBUF, Address 0x99). The ninth bit must be written to TB8 (Bit 3) in the serial communications control Register Bit Description SFR (SCON, 0x98). ...
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Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible. Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 control SFR (T2CON, Address 0xC8). The baud rates for ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula: ⎛ f ⎜ = × CORE SBAUDF 64 ⎜ + × × DIV SBTH ...
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SERIAL PERIPHERAL INTERFACE (SPI) The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 integrate a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that eight bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, allowing users ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 148. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8) Bit Address Mnemonic Default [7:6] 0xEF to Reserved 0 0xEE 5 0xED INTMOD 0 4 0xEC AUTO_SS 1 3 0xEB SS_EN 0 2 0xEA RxOFW 0 [1:0] 0xE9 to SPIR ...
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Table 149. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9) Bit Mnemonic Default Description 7 SPICONT 0 Master mode, SPI continuous transfer mode enable bit. SPICONT SPIEN 0 SPI interface enable bit. SPIEN SPIODO 0 ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 150. SPI Interrupt Status SFR (SPISTAT, Address 0xEA) Bit Mnemonic Default Description 7 BUSY 0 SPI peripheral busy flag. BUSY MMERR 0 SPI multimaster error flag. MMERR SPIRxOF 0 SPI receive overflow ...
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In both master and slave modes, the data is transmitted on one edge of the SCLK signal and sampled on the other important, therefore, that the SPICPHA and SPICPOL bits be configured the same for the master and ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SPI INTERRUPT AND STATUS FLAGS The SPI interface has several status flags that indicate the status of the double-buffered receive and transmit registers. Figure 111 shows when the status and interrupt flags are raised. The transmit interrupt occurs when ...
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I C-COMPATIBLE INTERFACE The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ 2 ADE7569 support a fully licensed I C interface. The I interface is implemented as a full hardware master. SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK (P0.6/SCLK/T0) is the serial clock. These ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 2 Table 154 Interrupt Status Register SFR (SPI2CSTAT, Address 0xEA) Bit Mnemonic Default 7 I2CBUSY 0 6 I2CNOACK 0 5 I2CRxIRQ 0 4 I2CTxIRQ 0 [3:2] I2CFIFOSTAT 0 1 I2CACC_ERR 0 0 I2CTxWR_ERR 0 READ AND WRITE ...
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I C RECEIVE AND TRANSMIT FIFOS 2 The I C peripheral has a 4-byte receive FIFO and a 4-byte transmit FIFO. The buffers reduce the overhead associated with 2 using the I C peripheral. Figure 115 shows the operation ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 I/O PORTS PARALLEL I/O The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 use three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available on-chip. ...
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I/O REGISTERS Table 156. Extended Port Configuration SFR (EPCFG, Address 0x9F) Bit Mnemonic 7 MOD38_FP21 6 MOD38_FP22 5 MOD38_FP23 4 MOD38_TxD 3 MOD38_CF1 2 MOD38_SSb 1 MOD38_MISO 0 MOD38_CF2 Table 157. Port 0 Weak Pull-Up Enable SFR (PINMAP0, Address 0xB2) ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 160. Port 0 SFR (P0, Address 0x80) Bit Bit Address Mnemonic 7 0x87 T1 6 0x86 T0 5 0x85 4 0x84 3 0x83 CF2 2 0x82 CF1 1 0x81 0 0x80 INT1 1 When an alternate function is ...
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Table 163. Port 0 Alternate Functions Pin No. Alternate Function P0.0 BCTRL external battery control input INT1 external interrupt INT1 wake-up from PSM2 operating mode P0.1 FP19 LCD segment pin P0.2 CF1 ADE calibration frequency output P0.3 CF2 ADE calibration ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, Address 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 weak pull-up Enable SFR (PINMAP0, Address 0xB2); they are enabled ...
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DETERMINING THE VERSION OF THE PART Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine whether users have the latest version of the part. The version of the ADE7116/ADE7156/ ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 OUTLINE DIMENSIONS 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 0.75 0.60 1.60 MAX 0. PIN 1 0.20 0.09 7° 3.5° 16 0° ...
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... ADE7566ASTZF16- ADE7569ACPZF16 No 2 ADE7569ACPZF16- ADE7569ASTZF8 No 2 ADE7569ASTZF8- ADE7569ASTZF16 No 2 ADE7569ASTZF16- ADE8052Z-PRG1 2 ADE8052Z-DWDL1 2 ADE8052Z-EMUL1 EVAL-ADE7169F16EBZ 2 2 EVAL-ADE7569F16EBZ 1 All models have rms LCD, and RTC RoHS Compliant Part. 3 The ADE7116 does not support battery and temperature ADC measurements. 4 The ADE7116 and the ADE7156 do not have internally adjustable LCD levels. ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 NOTES Rev Page 150 of 152 ...
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NOTES ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev Page 151 of 152 ...
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...