PIC10F200-I/P Microchip Technology, PIC10F200-I/P Datasheet - Page 36

• Manufacturer Part Number: PIC10F200-I/P
• Description: IC PIC MCU FLASH 256X12 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 10Fr

Specifications of PIC10F200-I/P

• Program Memory Type: FLASH
• Program Memory Size: 384B (256 x 12)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 3
• Ram Size: 16 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC10F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 16 B
• Interface Type: USB
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162059 - HEADER INTRFC MPLAB ICD2 8/14PINAC164037 - MODULE SKT 6L PROMATE II SOT23
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC10F200/202/204/206
FIGURE 7-2:
FIGURE 7-3:
TABLE 7-1:
7.1
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (T
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
7.1.1
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of an external clock with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-4). Therefore, it is necessary for T0CKI or the
comparator output to be high for at least 2 T
DS41239D-page 34
01h
07h
N/A
N/A
Legend:
Note 1:
Address
PC
(Program
Counter)
Instruction
Fetch
Timer0
Instruction
Executed
PC
(Program
Counter)
Instruction
Fetch
Timer0
Instruction
Executed
Using Timer0 with an External
Clock (PIC10F204/206)
TMR0
CMCON0
OPTION
TRISGPIO
Shaded cells not used by Timer0. – = unimplemented, x = unknown, u = unchanged.
The TRIS of the T0CKI pin is overridden when T0CS = 1.
EXTERNAL CLOCK
SYNCHRONIZATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Name
T0
T0
PC – 1
PC – 1
REGISTERS ASSOCIATED WITH TIMER0
(1)
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Timer0 – 8-bit Real-Time Clock/Counter
CMPOUT
GPWU
Bit 7
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
—
T0 + 1
PC
PC
COUTEN
GPPU
Bit 6
—
OSC
Write TMR0
executed
Write TMR0
executed
T0 + 2
) synchroniza-
PC + 1
PC + 1
T0CS
OSC
Bit 5
POL
—
(and a
CMPT0CS CMPON CNREF CPREF
Read TMR0
reads NT0
Read TMR0
reads NT0
T0SE
Bit 4
—
PC + 2
PC + 2
I/O Control Register
Bit 3
PSA
NT0
small RC delay of 2 Tt0H) and low for at least 2 T
(and a small RC delay of 2 Tt0H). Refer to the electrical
specification of the desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI or the comparator
output to have a period of at least 4 T
RC delay of 4 Tt0H) divided by the prescaler value. The
only requirement on T0CKI or the comparator output
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0
PC + 3
PC + 3
Bit 2
PS2
Read TMR0
reads NT0
Read TMR0
reads NT0
Bit 1
PS1
PC + 4
PC + 4
CWU
Bit 0
PS0
© 2007 Microchip Technology Inc.
NT0 + 1
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 1
PC+5
PC + 5
xxxx xxxx
1111 1111
1111 1111
---- 1111
Power-On
Value on
Reset
OSC
Read TMR0
reads NT0 + 2
Read TMR0
reads NT0 + 2
NT0 + 2
NT0 + 1
(and a small
PC + 6
PC + 6
uuuu uuuu
uuuu uuuu
1111 1111
---- 1111
All Other
Value on
Resets
OSC