Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 13

IC 8MHZ Z8500 CMOS SCC 44-PLCC

Z85C3008VSG

Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Datasheets

Specifications of Z85C3008VSG

Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG

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PS011705-0608
Z85C30
Z80C30
A/B
Channel A/Channel B (input) —
Write operation occurs.
CE
Chip Enable (input, active Low) —
operation.
D7–D0
Data Bus (bidirectional, tri-state) —
the SCC.
D/C
Data/Control Select (input) —
or from the SCC. A High indicates a data transfer; a Low indicates a command.
RD
Read (input, active Low) —
selected, enables the SCC’s bus drivers. During the Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the bus if the SCC is the highest priority device
requesting an interrupt.
WR
Write (input, active Low) —
operation. The coincidence of RD and WR is interpreted as a reset.
AD7–AD0
Address/Data Bus (bidirectional, active High, Tri-state) —
carry register addresses to the SCC as well as data or control information.
AS
Address Strobe (input, active Low) —
rising edge of this signal.
CS0
Chip Select 0 (input, active Low) —
addresses on AD7–AD0 and must be active for the intended bus transaction to occur.
This signal indicates a Read operation and when the SCC is
When the SCC is selected, this signal indicates a Write
This signal defines the type of information transferred to
This signal selects the channel in which the Read or
CMOS SCC Serial Communications Controller
This signal selects the SCC for a Read or Write
This signal is latched concurrently with the
These lines carry data and command to and from
Addresses on AD7–AD0 are latched by the
These multiplexed lines
Product Specification
General Description
9

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