Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 25

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

PS011705-0608
Both CRC-16 (X
polynomials are supported. Either polynomial can be selected in all Synchronous modes.
You can preset the CRC generator and checker to all 1’s or all 0’s. The SCC also provides
a feature that automatically transmits CRC data when no other data is available for trans-
mission. This feature allows for high speed transmissions under DMA control, with no
need for CPU intervention at the end of a message.
When there is no data or CRC to send in Synchronous modes, the transmitter inserts 6-,8-,
or 16-bit sync characters, regardless of the programmed character length.
SDLC Mode
The SCC supports Synchronous bit-oriented protocols, such as SDLC and HDLC, by
performing automatic flag sending, zero insertion, and CRC generation. A special
command is used to abort a frame in transmission. At the end of a message, the SCC auto-
matically transmits the CRC and trailing flag when the transmitter underruns. The trans-
mitter can also be programmed to send an idle line consisting of continuous flag characters
or a steady marking condition.
If a transmit underrun occurs in the middle of a message, an external/status interrupt warns
the CPU of this status change, issuing an abort. The SCC can also be programmed to send
an abort itself in case of an underrun, relieving the CPU of this task. One to eight bits per
character can be sent, allowing reception of a message with no prior information about the
character structure in the information field of a frame.
The receiver automatically acquires synchronization on the leading flag of a frame in
SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be programmed to search for frames addressed by
a single byte (or four bits within a byte) of a user-selected address or to a global broadcast
address. In this mode, frames not matching either the user-selected or broadcast address
are ignored.
The number of address bytes are extended under software control. For receiving data, an
interrupt on the first received character, or an interrupt on every character, or on special
condition only (end-of-frame) can be selected. The receiver automatically deletes all 0’s
inserted by the transmitter during character assembly CRC is also calculated and is auto-
matically checked to validate frame transmission. At the end of transmission, the status of
a received frame is available in the status registers. In SDLC mode, the SCC must be pro-
grammed to use the SDLC CRC polynomial, but the generator and checker can be preset
to all 1’s or all 0’s. The CRC inverts before transmission and the receiver checks against
the bit pattern 0001110100001111.
NRZ, NRZI or FM coding can be used in any 1 x mode. The parity options available in
Asynchronous modes are available in Synchronous modes.
SDLC Loop Mode
The SCC supports SDLC Loop mode in addition to normal SDLC. In an SDLC Loop, a
primary controller station manages the message traffic flow on the loop and any number of
secondary stations. In SDLC Loop mode, the SCC performs the functions of a secondary
16
+ X
15
+ X
12
+1) and CCITT (X
CMOS SCC Serial Communications Controller
16
+ X
12
+ X
Product Specification
5
+ 1) error-checking
Functional Description
21