EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 124

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
UART Line Status Registers
This register is used to show the status of UART interrupts and registers. See
Table 63. UART Line Status Registers (UART0_LSR = 00C5h, UART1_LSR = 00 D5h)
Bit
Position
3
OUT2
2
OUT1
1
RTS
0
DTR
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
7
ERR
Value Description
Value Description
0–1
0–1
0–1
0–1
0
1
No function in normal operation.
In LOOP BACK mode, this bit is connected to the DCD bit in
the UART Status Register.
No function in normal operation.
In LOOP BACK mode, this bit is connected to the RI bit in the
UART Status Register.
Request to Send.
In normal operation, the RTS output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the CTS bit in
the UART Status Register.
Data Terminal Ready.
In normal operation, the DTR output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the DSR bit
in the UART Status Register.
Always 0 when operating with the FIFO disabled. With the
FIFO enabled, this bit is reset when the UARTx_LSR register is
read and there are no more bytes with error status in the FIFO.
Error detected in the FIFO. There is at least 1 parity, framing or
break indication error in the FIFO.
R
7
0
R
6
1
R
5
1
Universal Asynchronous Receiver/Transmitter
R
4
0
R
3
0
Product Specification
R
2
0
eZ80L92 MCU
R
1
0
Table
63.
R
0
0
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