EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 137

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
SPI Functional Description
Enable (To Slave)
Sample Input
Sample Input
Table 68. SPI Clock Phase and Clock Polarity Operation
When a master transmits to a slave device via the MOSI signal, the slave device responds
by sending data to the master via the master's MISO signal. The resulting implication is a
full-duplex transmission, with both data out and data in synchronized with the same clock
signal. Thus the byte transmitted is replaced by the byte received and eliminates the
requirement for separate transmit-empty and receive-full status bits. A single status bit,
SPIF, is used to signify that the I/O operation is completed, see
(SPI_SR)
CPHA
0
0
1
1
on page
CPOL
MSB
0
1
0
1
136.
MSB
1
Figure 29. SPI Timing
6
Transmit
Falling
Falling
6
Rising
Rising
Edge
2
SCK
Number of Cycles on the SCK Signal
5
5
3
4
Receive
Falling
Falling
Rising
Rising
Edge
4
SCK
4
3
3
5
2
State
SCK
High
High
Low
Low
Idle
2
6
SPI Status Register
Product Specification
1
Serial Peripheral Interface
1
7
Characters?
LSB
eZ80L92 MCU
Between
SS High
LSB
Yes
Yes
No
No
8
131